SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

15.2.33.1 MMC_PVSDR25SDR50 Register (Offset = 268h) [reset = 0h]

Preset Value for SDR25 and SDR50 speed modes.

Table 5-1828 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0268h

Figure 5-902 MMC_PVSDR25SDR50 Name Register

Table 5-1829 MMC_PVSDR25SDR50 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	SDR50DS_SEL	R	0h	Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 3 Driver Type D is Selected. 2 Driver Type C is Selected. 1 Driver Type A is Selected. 0 Driver Type B is Selected.
29:27	RESERVED1	R	0h
26	SDR50CLKGEN_SEL	R	0h	Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator. 1 Programmable Clock Generator. 0 Host Controller Ver2.00 Compatible Clock Generator.
25:16	SDR50SDCLK_SEL	R	0h	SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
15:14	SDR25DS_SEL	R	0h	Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 3 Driver Type D is Selected. 2 Driver Type C is Selected. 1 Driver Type A is Selected. 0 Driver Type B is Selected.
13:11	RESERVED	R	0h
10	SDR25CLKGEN_SEL	R	0h	Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator. 1 Programmable Clock Generato. 0 Host Controller Ver2.00 Compatible Clock Generator.
9:0	SDR25SDCLK_SEL	R	0h	SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.