SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ADC Offset Trim Register.
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| Instance Name | Physical Address |
|---|---|
| ADC0_G0_G5 | 502C 0076h |
| ADC1_G0_G5 | 502C 1076h |
| ADC2_G0_G5 | 502C 2076h |
| ADC3_G0_G5 | 502C 3076h |
| ADC4_G0_G5 | 502C 4076h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| OFFTRIM12BSEODD | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| OFFTRIM | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:8 | OFFTRIM12BSEODD | R/W | 0h | If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim when the ADC is in 12-bit single-ended mode for odd channels. Range is +127 steps to -128 steps [2's compliment format]. Regardless of the converter resolution, the size of each trim step is [VREFHI-VREFLO]/65536. |
| 7:0 | OFFTRIM | R/W | 0h | ADC Offset Trim. Adjusts the conversion results of the converter up or down to account for offset error in the ADC. A different offset trim is required for each combination of resolution and signal mode. If ADCCTL2.OFFTRIMMODE = 0, then using the AdcSetMode function to set the resolution and signal mode will ensure that the correct offset trim is loaded into this register. If ADCCLT2.OFFTRIMMODE = 1, then this register will supply offset trim only when the ADC is in 12-bit single-ended mode and only for even channels. Range is +127 steps to -128 steps [2's compliment format]. Regardless of the converter resolution, the size of each trim step is [VREFHI-VREFLO]/65536. |