SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.217 ICSSM_PR1_ICSS_UART_UART_SLV_FCR Register

2.2.217.1 ICSSM_PR1_ICSS_UART_UART_SLV_FCR Register (Offset = 8h) [reset = 0h]

FIFO Control Register (write only)
The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR), which is a read-only register.

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Table 4-855 Instance Table

Instance Name	Physical Address
ICSSM0	4802 8008h

Figure 4-411 ICSSM_PR1_ICSS_UART_UART_SLV_FCR Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RXFITL		RESERVED		DMAMODE1	TXCLR	RXCLR	FIFOEN
W		NONE		W	W	W	W
0h		0h		1h	0h	0h	0h

Table 4-856 ICSSM_PR1_ICSS_UART_UART_SLV_FCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED	NONE	0h	Reserved
7:6	RXFITL	W	0h	Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. 3h 14 bytes 2h 8 bytes 1h 4 bytes 0h 1 byte
5:4	RESERVED	NONE	0h	Reserved
3	DMAMODE1	W	1h	DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. 1h DMA MODE 1 is enabled 0h DMA MODE 1 is disabled
2	TXCLR	W	0h	Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. 1h Clears transmitter FIFO and resets the transmitter FIFO counter. The shift register is not cleared. 0h No effect
1	RXCLR	W	0h	Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. 1h Clears receiver FIFO and resets the receiver FIFO counter. The shift register is not cleared. 0h No effect
0	FIFOEN	W	0h	Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. 1h FIFO mode. The transmitter and receiver FIFOs are enabled. 0h Non-FIFO mode. The transmitter and receiver FIFOs are disabled, and the FIFO pointers are cleared.