SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.6.2.10 ECAP_ECEINT Register

6.2.10.1 ECAP_ECEINT Register (Offset = 2Ch) [reset = 0h]

The interrupt enable bits (CEVT1, ...) block any of the selected events from generating an interrupt. Events will still be latched into the flag bit (ECFLG register) and can be forced/cleared via the ECFRC/ECCLR registers.

The proper procedure for configuring peripheral modes and interrupts is as follows:

- Disable global interrupts
- Stop eCAP counter
- Disable eCAP interrupts
- Configure peripheral registers
- Clear spurious eCAP interrupt flags
- Enable eCAP interrupts
- Start eCAP counter
- Enable global interrupts.

Return to Summary Table

Table 3-480 Instance Table

Instance Name	Physical Address
ECAP0	5024 002Ch
ECAP1	5024 102Ch
ECAP2	5024 202Ch
ECAP3	5024 302Ch
ECAP4	5024 402Ch
ECAP5	5024 502Ch
ECAP6	5024 602Ch
ECAP7	5024 702Ch
ECAP8	5024 802Ch
ECAP9	5024 902Ch

Figure 3-232 ECAP_ECEINT Name Register

15	14	13	12	11	10	9	8
RESERVED_2			MUNIT_2_ERROR_EVT2	MUNIT_2_ERROR_EVT1	MUNIT_1_ERROR_EVT2	MUNIT_1_ERROR_EVT1	HRERROR
R			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
CTR_EQ_CMP	CTR_EQ_PRD	CTROVF	CEVT4	CEVT3	CEVT2	CEVT1	RESERVED_1
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R
0h	0h	0h	0h	0h	0h	0h	0h

Table 3-481 ECAP_ECEINT Register Field Descriptions

Bit	Field	Type	Reset	Description
15:13	RESERVED_2	R	0h	Reserved
12	MUNIT_2_ERROR_EVT2	R/W	0h	Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 2 interrupt 1 : Enable Monitoring unit 2 error event 2 interrupt
11	MUNIT_2_ERROR_EVT1	R/W	0h	Monitoring unit 2 error event 2 interrupt enable 0 : Disable Monitoring unit 2 error event 1 interrupt 1 : Enable Monitoring unit 2 error event 1 interrupt
10	MUNIT_1_ERROR_EVT2	R/W	0h	Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 2 interrupt 1 : Enable Monitoring unit 1 error event 2 interrupt
9	MUNIT_1_ERROR_EVT1	R/W	0h	Monitoring unit 1 error event 1 interrupt enable 0 : Disable Monitoring unit 1 error event 1 interrupt 1 : Enable Monitoring unit 1 error event 1 interrupt
8	HRERROR	R/W	0h	High resolution error interrupt enable 1 Enable High Resolution Error as an Interrupt source 0 Disable High Resolution Error as an Interrupt source
7	CTR_EQ_CMP	R/W	0h	Counter Equal Compare Interrupt Enable 1 Enable Compare Equal as an Interrupt source 0 Disable Compare Equal as an Interrupt source
6	CTR_EQ_PRD	R/W	0h	Counter Equal Period Interrupt Enable 1 Enable Period Equal as an Interrupt source 0 Disable Period Equal as an Interrupt source
5	CTROVF	R/W	0h	Counter Overflow Interrupt Enable 1 Enable counter Overflow as an Interrupt source 0 Disabled counter Overflow as an Interrupt source
4	CEVT4	R/W	0h	Capture Event 4 Interrupt Enable 1 Capture Event 4 Interrupt Enable 0 Disable Capture Event 4 as an Interrupt source
3	CEVT3	R/W	0h	Capture Event 3 Interrupt Enable 1 Enable Capture Event 3 as an Interrupt source 0 Disable Capture Event 3 as an Interrupt source
2	CEVT2	R/W	0h	Capture Event 2 Interrupt Enable 1 Enable Capture Event 2 as an Interrupt source 0 Disable Capture Event 2 as an Interrupt source
1	CEVT1	R/W	0h	Capture Event 1 Interrupt Enable 1 Enable Capture Event 1 as an Interrupt source 0 Disable Capture Event 1 as an Interrupt source
0	RESERVED_1	R	0h	Reserved