SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

12.2.59.1 CFG_RXF1S Register (Offset = 2B4h) [reset = 0h]

Rx FIFO 1 Status register. FIFO 1 message lost/full indication, put index, get index and fill level.

Table 5-1490 Instance Table

Figure 5-735 CFG_RXF1S Name Register

Table 5-1491 CFG_RXF1S Register Field Descriptions

Bit	Field	Type	Reset	Description
31:26	NU54	R	0h	Reserved
25	RF1L	R	0h	Rx FIFO 1 Message Lost This bit is a copy of interrupt flag MCAN_IR[7] RF1L. When the MCAN_IR[7] RF1L flag is reset, this bit is also reset. 1'b0 = No Rx FIFO 1 message lost 1'b1 = Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero Note: OverWriting the oldest message when the MCAN_RXF1C[31] F1OM = 1'b1 will not set this flag.
24	F1F	R	0h	Rx FIFO 1 Full
23:22	NU53	R	0h	Reserved
21:16	F1PI	R	0h	Rx FIFO 1 Put Index
15:14	NU52	R	0h	Reserved
13:8	F1GI	R	0h	Rx FIFO 1 Get Index
7	NU51	R	0h	Reserved
6:0	F1FL	R	0h	Rx FIFO 1 Fill Level