SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.10.2.9 FSI_TX_CFG_TX_PING_CTRL_ALT1 Register

10.2.9.1 FSI_TX_CFG_TX_PING_CTRL_ALT1 Register (Offset = 14h) [reset = 0h]

Transmit ping control register.

Table 3-1084 Instance Table

Instance Name	Physical Address
FSI_TX0	5028 0014h
FSI_TX1	5028 1014h
FSI_TX2	502A 0014h
FSI_TX3	502A 1014h

Figure 3-510 FSI_TX_CFG_TX_PING_CTRL_ALT1 Name Register

15	14	13	12	11	10	9	8
RESERVED_1							EXT_TRIG_SEL
R							R/W
0h							0h
7	6	5	4	3	2	1	0
EXT_TRIG_SEL					EXT_TRIG_EN	TIMER_EN	CNT_RST
R/W					R/W	R/W	R/W
0h					0h	0h	0h

Table 3-1085 FSI_TX_CFG_TX_PING_CTRL_ALT1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:9	RESERVED_1	R	0h	Reserved
8:3	EXT_TRIG_SEL	R/W	0h	External Trigger Select bits This bitfield will select one of the 64 external trigger inputs to as the source to generate a ping frame. A ping frame will only be generated if the EXT_TRIG_EN bit is set. 0h[R/W] = Trigger 1 will be used to generate a ping frame. 1h[R/W] = Trigger 2 will be used to generate a ping frame. .. 3Fh [R/W] = Trigger 64 will be used to generate a ping frame.
2	EXT_TRIG_EN	R/W	0h	External Trigger Enable bit This bit will allow the external trigger logic to generate a ping frame. 0h[R/W] = External triggers will not be used to generate ping frames. 1h[R/W] = The selected external trigger [selected by EXT_TRIG_SEL bits] will be able to generate a ping frame. The ping timer will be ignored if this bit is set.
1	TIMER_EN	R/W	0h	Ping Timer Enable bit This bit will enable the ping timer for generating periodic ping frames. 0h[R/W] = The ping timer is disabled and will not generate ping frames. 1h[R/W] = The ping timer is enabled and can be used to generate ping frames.Once the timer count reaches the value set by the TX_PING_TO_REF register, it will initiate a ping frame transmission. Note: If the ping timer is used, EXT_TRIG_EN should not be set as it will override this function.
0	CNT_RST	R/W	0h	Ping Counter Reset bit Writing a 1 to this bit will reset the ping counter to 0. The counter will stay in reset as long as this bit is set to 1. This bit needs to be cleared to 0 to use the counter. 0h[R/W] = Clear the CNT_RST. 1h[R/W] = The ping counter will be reset to 0.