SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.21.1 CMPSSA_COMPLOCK Register (Offset = 34h) [reset = 0h]

CMPSS Lock Register.

Table 3-381 Instance Table

Figure 3-187 CMPSSA_COMPLOCK Name Register

Table 3-382 CMPSSA_COMPLOCK Register Field Descriptions

Bit	Field	Type	Reset	Description
15:5	RESERVED_1	R	0h	Reserved
4	TEST	R/W1TS	0h	TEST Lock. This bit, when set, will prevent any further writes to the any undocumented registers that may effect the performance/behavior of this block. Once set this bit can only be cleared by a reset.
3	CTRIP	R/W1TS	0h	Lock write-access to the CTRIPxFILTCTL and CTRIPxFILCLKCTL registers. 0 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are not locked. Write 0 to this bit has no effect. 1 CTRIPxFILCTL and CTRIPxFILCLKCTL registers are locked. Only a system reset can clear this bit.
2	DACCTL	R/W1TS	0h	Lock write-access to the DACCTL register. 0 DACCTL register is not locked. Write 0 to this bit has no effect. 1 DACCTL register is locked. Only a system reset can clear this bit.
1	COMPHYSCTL	R/W1TS	0h	Lock write-access to the COMPHYSCTL register. 0 COMPHYSCTL register is not locked. Write 0 to this bit has no effect. 1 COMPHYSCTL register is locked. Only a system reset can clear this bit.
0	COMPCTL	R/W1TS	0h	Lock write-access to the COMPCTL register. 0 COMPCTL register is not locked. Write 0 to this bit has no effect. 1 COMPCTL register is locked. Only a system reset can clear this bit.