SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.204 ICSSM_PR1_ICSS_UART_UART_SLV_IER Register

2.2.204.1 ICSSM_PR1_ICSS_UART_UART_SLV_IER Register (Offset = 4h) [reset = 0h]

The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the CPU.

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Table 4-829 Instance Table

Instance Name	Physical Address
ICSSM0	4802 8004h

Figure 4-398 ICSSM_PR1_ICSS_UART_UART_SLV_IER Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED				EDSSI	ELSI	ETBEI	ERBI
NONE				R/W	R/W	R/W	R/W
0h				0h	0h	0h	0h

Table 4-830 ICSSM_PR1_ICSS_UART_UART_SLV_IER Register Field Descriptions

Bit	Field	Type	Reset	Description
31:4	RESERVED	NONE	0h	Reserved
3	EDSSI	R/W	0h	Enable for Modem Status Interrupt
2	ELSI	R/W	0h	Enable for Receiver Line Status Interrupt 1h Received line status is enabled 0h Receiver line status interrupt is disabled.
1	ETBEI	R/W	0h	Enable for Transmitter Holding Register Empty Interrupt 1h Transmitter holding register empty interrupt is enabled. 0h Transmitter holding register empty interrupt is disabled.
0	ERBI	R/W	0h	Enable for Receiver Data Available Interrupt 1h Receiver data available interrupt and character timeout indication interrupt is enabled. 0h Receiver data available interrupt and character timeout indication interrupt is disabled.