SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Timestamp Counter Value.
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| Instance Name | Physical Address |
|---|---|
| MCAN0 | 5260 8224h |
| MCAN1 | 5261 8224h |
| MCAN2 | 5262 8224h |
| MCAN3 | 5263 8224h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU22 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU22 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TSC | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TSC | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | NU22 | R | 0h | Reserved |
| 15:0 | TSC | R/W | 0h | Timestamp Counter The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx). When the MCAN_TSCC[1-0] TSS = 2'b01, the Timestamp Counter is incremented in multiples of CAN bit times [1-16] depending on the configuration of the MCAN_TSCC[19-16] TCP field. A wrap around sets interrupt flag MCAN_IR[16] TSW. Write access resets the counter to zero. When the MCAN_TSCC[1-0] TSS = 2'b10, the MCAN_TSCV[15-0] TSC field reflects the external Timestamp Counter value. A write access has no impact. Note: A 'wrap around' is a change of the Timestamp Counter value from non-zero to zero not caused by write access to the MCAN_TSCV register. |