SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.11.2.6 LIN_SCISETINTLVL Register

11.2.6.1 LIN_SCISETINTLVL Register (Offset = 14h) [reset = 0h]

The SCISETINTLVL register is used to map individual interrupt sources to the INT1 interrupt line.

Table 5-1302 Instance Table

Instance Name	Physical Address
LIN0	5240 0014h
LIN1	5240 1014h
LIN2	5240 2014h
LIN3	5240 3014h
LIN4	5240 4014h

Figure 5-644 LIN_SCISETINTLVL Name Register

31	30	29	28	27	26	25	24
SETBEINTLVL	SETPBEINTLVL	SETCEINTLVL	SETISFEINTLVL	SETNREINTLVL	SETFEINTLVL	SETOEINTLVL	SETPEINTLVL
R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED_7					RESERVED_6	RESERVED_5
R					R	R
0h					0h	0h
15	14	13	12	11	10	9	8
RESERVED_4		SETIDINTLVL	RESERVED_3			SETRXINTOVO	SETTXINTLVL
R		R/W1TS	R			R/W1TS	R/W1TS
0h		0h	0h			0h	0h
7	6	5	4	3	2	1	0
SETTOA3WUSINTLVL	SETTOAWUSINTLVL	RESERVED_2	SETTIMEOUTINTLVL	RESERVED_1		SETWAKEUPINTLVL	SETBRKDTINTLVL
R/W1TS	R/W1TS	R	R/W1TS	R		R/W1TS	R/W1TS
0h	0h	0h	0h	0h		0h	0h

Table 5-1303 LIN_SCISETINTLVL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	SETBEINTLVL	R/W1TS	0h	Set Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
30	SETPBEINTLVL	R/W1TS	0h	Set Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
29	SETCEINTLVL	R/W1TS	0h	Set Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
28	SETISFEINTLVL	R/W1TS	0h	Set Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
27	SETNREINTLVL	R/W1TS	0h	Set No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
26	SETFEINTLVL	R/W1TS	0h	Set Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
25	SETOEINTLVL	R/W1TS	0h	Set Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
24	SETPEINTLVL	R/W1TS	0h	Set Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity error interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
23:19	RESERVED_7	R	0h	Reserved
18	RESERVED_6	R	0h	Reserved
17:16	RESERVED_5	R	0h	Reserved
15:14	RESERVED_4	R	0h	Reserved
13	SETIDINTLVL	R/W1TS	0h	Set ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
12:10	RESERVED_3	R	0h	Reserved
9	SETRXINTOVO	R/W1TS	0h	Set Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
8	SETTXINTLVL	R/W1TS	0h	Set Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
7	SETTOA3WUSINTLVL	R/W1TS	0h	Set Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
6	SETTOAWUSINTLVL	R/W1TS	0h	Set Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
5	RESERVED_2	R	0h	Reserved
4	SETTIMEOUTINTLVL	R/W1TS	0h	Set Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT1 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
3:2	RESERVED_1	R	0h	Reserved
1	SETWAKEUPINTLVL	R/W1TS	0h	Set Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT1 line. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.
0	SETBRKDTINTLVL	R/W1TS	0h	Set Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT1 line. This field is writable in SCI mode only. 1 Interrupt level mapped to INT1 line. 0 Interrupt level mapped to INT0 line.