SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.14.2.6 MCSPI_IRQSTATUS Register

14.2.6.1 MCSPI_IRQSTATUS Register (Offset = 118h) [reset = 0h]

The interrupt status regroups all the status of the module internal events that can generate an interrupt .

Table 5-1707 Instance Table

Instance Name	Physical Address
MCSPI0	5220 0118h
MCSPI1	5220 1118h
MCSPI2	5220 2118h
MCSPI3	5220 3118h
MCSPI4	5220 4118h

Figure 5-842 MCSPI_IRQSTATUS Name Register

31	30	29	28	27	26	25	24
RESERVED_8
R
0h
23	22	21	20	19	18	17	16
RESERVED_8						EOW	WKS
R						R/W1TS	R/W1TS
0h						0h	0h
15	14	13	12	11	10	9	8
RESERVED_7	RX3_FULL	TX3_UNDERFLOW	TX3_EMPTY	RESERVED_9	RX2_FULL	TX2_UNDERFLOW	TX2_EMPTY
R	R/W1TS	R/W1TS	R/W1TS	R	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
RESERVED_10	RX1_FULL	TX1_UNDERFLOW	TX1_EMPTY	RX0_OVERFLOW	RX0_FULL	TX0_UNDERFLOW	TX0_EMPTY
R	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS	R/W1TS
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-1708 MCSPI_IRQSTATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED_8	R	0h	Reads returns 0
17	EOW	R/W1TS	0h	End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined by MCSPI_XFERLEVEL[WCNT] 1 Event status bit is reset 0 Event false
16	WKS	R/W1TS	0h	Wake Up event in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 1 Event is pending 0 Event status bit unchanged
15	RESERVED_7	R	0h	Reads returns 0
14	RX3_FULL	R/W1TS	0h	Receiver register is full or almost full Only when Channel 3 is enabled 1 Event is pending 0 Event status bit unchanged
13	TX3_UNDERFLOW	R/W1TS	0h	Transmitter register underflow Only when Channel 3 is enabled The transmitter register is empty [not updated by Host or DMA with new data] before its time slot assignment Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled 1 Event is pending 0 Event status bit unchanged
12	TX3_EMPTY	R/W1TS	0h	Transmitter register is empty or almost empty Note: Enabling the channel automatically rises this event 1 Event is pending 0 Event status bit unchanged
11	RESERVED_9	R	0h	Reads returns 0
10	RX2_FULL	R/W1TS	0h	Receiver register full or almost full Channel 2 1 Event is pending 0 Event status bit unchanged
9	TX2_UNDERFLOW	R/W1TS	0h	Transmitter register underflow Channel 2 1 Event is pending 0 Event status bit unchanged
8	TX2_EMPTY	R/W1TS	0h	Transmitter register empty or almost empty Channel 2 1 Event is pending 0 Event status bit unchanged
7	RESERVED_10	R	0h	Reads returns 0
6	RX1_FULL	R/W1TS	0h	Receiver register full or almost full Channel 1 1 Event is pending 0 Event status bit unchanged
5	TX1_UNDERFLOW	R/W1TS	0h	Transmitter register underflow Channel 1 1 Event is pending 0 Event status bit unchanged
4	TX1_EMPTY	R/W1TS	0h	Transmitter register empty or almost empty Channel 1 1 Event is pending 0 Event status bit unchanged
3	RX0_OVERFLOW	R/W1TS	0h	Receiver register overflow [target mode only] Channel 0 1 Event is pending 0 Event status bit unchanged
2	RX0_FULL	R/W1TS	0h	Receiver register full or almost full Channel 0 1 Event is pending 0 Event status bit unchanged
1	TX0_UNDERFLOW	R/W1TS	0h	Transmitter register underflow Channel 0 1 Event is pending 0 Event status bit unchanged
0	TX0_EMPTY	R/W1TS	0h	Transmitter register empty or almost empty Channel 0 1 Event is pending 0 Event status bit unchanged