SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Enet Port N Control
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Offset = Base + (k * 1000h); where k = 0 to 1d
| Instance Name | Physical Address |
|---|---|
| CPSW0 | 5282 2004h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | EST_PORT_EN | RESERVED | |||||
| NONE | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RX_ECC_ERR_EN | TX_ECC_ERR_EN | RESERVED | TX_LPI_CLKSTOP_EN | RESERVED | |||
| R/W | R/W | NONE | R/W | NONE | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DSCP_IPV6_EN | DSCP_IPV4_EN | RESERVED | ||||
| NONE | R/W | R/W | NONE | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17 | EST_PORT_EN | R/W | 0h | EST Port Enable 0 - EST is disabled on the port. 1 - EST is enabled on the port (Does not take effect until the CPSW level est_en is set). |
| 16 | RESERVED | NONE | 0h | Reserved |
| 15 | RX_ECC_ERR_EN | R/W | 0h | This bit must be set to enable receive ECC error operations on the port. |
| 14 | TX_ECC_ERR_EN | R/W | 0h | This bit must be set to enable transmit ECC error operations on the port. |
| 13 | RESERVED | NONE | 0h | Reserved |
| 12 | TX_LPI_CLKSTOP_EN | R/W | 0h | Transmit LPI Clock Stop Enable - When set this bit causes the transmit output clock (GMII_GMTCLK_O) to be stopped when the transmit LPI state is entered if EEE is enabled. |
| 11:3 | RESERVED | NONE | 0h | Reserved |
| 2 | DSCP_IPV6_EN | R/W | 0h | IPv6 DSCP enable 0 - Ipv6 DSCP priority mapping is disabled. 1 - Ipv6 DSCP priority mapping is enabled. |
| 1 | DSCP_IPV4_EN | R/W | 0h | IPv4 DSCP enable 0 - Ipv4 DSCP priority mapping is disabled. 1 - Ipv4 DSCP priority mapping is enabled. |
| 0 | RESERVED | NONE | 0h | Reserved |