SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.2.50 ADC_CFG_ADCINTOVF Register

2.2.50.1 ADC_CFG_ADCINTOVF Register (Offset = Ah) [reset = 0h]

ADC Interrupt Overflow Register.

Table 3-103 Instance Table

Instance Name	Physical Address
ADC0_G0_G5	502C 000Ah
ADC1_G0_G5	502C 100Ah
ADC2_G0_G5	502C 200Ah
ADC3_G0_G5	502C 300Ah
ADC4_G0_G5	502C 400Ah

Figure 3-50 ADC_CFG_ADCINTOVF Name Register

15	14	13	12	11	10	9	8
RESERVED_1
R
0h
7	6	5	4	3	2	1	0
RESERVED_1				ADCINT4	ADCINT3	ADCINT2	ADCINT1
R				R	R	R	R
0h				0h	0h	0h	0h

Table 3-104 ADC_CFG_ADCINTOVF Register Field Descriptions

Bit	Field	Type	Reset	Description
15:4	RESERVED_1	R	0h	Reserved
3	ADCINT4	R	0h	ADC Interrupt 4 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.
2	ADCINT3	R	0h	ADC Interrupt 3 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.
1	ADCINT2	R	0h	ADC Interrupt 2 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.
0	ADCINT1	R	0h	ADC Interrupt 1 Overflow Flags Indicates if an overflow occurred when generating ADCINT pulses. If the respective ADCINTFLG bit is set and a selected additional EOC trigger is generated, then an overflow condition occurs. 0 No ADC interrupt overflow event detected. 1 ADC Interrupt overflow event detected. The overflow bit does not care about the continuous mode bit state. An overflow condition is generated irrespective of this mode selection.