SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.158.1 MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_STATUS_RAW Register (Offset = 18098h) [reset = 0h]

Raw status for uncorrectable error from R5SS0 CORE0 Memories.

Table 2-317 Instance Table

Instance Name	Physical Address
MSS_CTRL	50D1 8098h

Figure 2-158 MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_STATUS_RAW Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED			R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DDATA_UNCORR_ERR	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DTAG_UNCORR_ERR	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B0TCM_UNCORR_ERR	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B1TCM_UNCORR_ERR	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_ATCM_UNCORR_ERR
NONE			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h

Table 2-318 MSS_CTRL_R5SS0_CORE0_ECC_UNCORR_ERRAGG_STATUS_RAW Register Field Descriptions

Bit	Field	Type	Reset	Description
31:5	RESERVED	NONE	0h	Reserved
4	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DDATA_UNCORR_ERR	R/W	0h	Raw Status of Interrupt from correctable error of corresponding CPU Set only if Interupt is unmasked in corresponding R5SS_CPU_ECC_UNCORR_ERRAGG_MASK register Wrie 0x1 to clear this interrupt.
3	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_DTAG_UNCORR_ERR	R/W	0h	Raw Status of Interrupt from correctable error of corresponding CPU Set only if Interupt is unmasked in corresponding R5SS_CPU_ECC_UNCORR_ERRAGG_MASK register Wrie 0x1 to clear this interrupt.
2	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B0TCM_UNCORR_ERR	R/W	0h	Raw Status of Interrupt from correctable error of corresponding CPU Set only if Interupt is unmasked in corresponding R5SS_CPU_ECC_UNCORR_ERRAGG_MASK register Wrie 0x1 to clear this interrupt.
1	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_B1TCM_UNCORR_ERR	R/W	0h	Raw Status of Interrupt from correctable error of corresponding CPU Set only if Interupt is unmasked in corresponding R5SS_CPU_ECC_UNCORR_ERRAGG_MASK register Wrie 0x1 to clear this interrupt.
0	R5SS0_CPU0_ECC_UNCORR_ERRAGG_STATUS_RAW_R5SS0_CPU0_ATCM_UNCORR_ERR	R/W	0h	Raw Status of Interrupt from correctable error of corresponding CPU Set only if Interupt is unmasked in corresponding R5SS_CPU_ECC_UNCORR_ERRAGG_MASK register Wrie 0x1 to clear this interrupt.