SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.336.1 ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECFRC Register (Offset = 34h) [reset = 0h]

ECAP INTERRUPT FORCING REGISTER.

Table 4-1093 Instance Table

Instance Name	Physical Address
ICSSM0	4803 0034h

Figure 4-530 ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECFRC Name Register

Table 4-1094 ICSSM_PR1_ICSS_ECAP0_ECAP_SLV_ECFRC Register Field Descriptions

Bit	Field	Type	Reset	Description
31:16	RESERVED	NONE	0h	Reserved
15:8	_RESV1	R	0h
7	CMPEQ	R/W	0h	FORCE COMPARE EQUAL: WRITING A 1 TO THIS BIT WILL SET THE CMPEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
6	PRDEQ	R/W	0h	FORCE PERIOD EQUAL: WRITING A 1 TO THIS BIT WILL SET THE PRDEQ FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
5	CNTOVF	R/W	0h	FORCE COUNTER OVERFLOW: WRITING A 1 TO THIS BIT WILL SET THE CNTOVF FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
4	CEVT4	R/W	0h	FORCE CAPTURE EVENT 4:WRITING A 1 TO THIS BIT WILL SET THE CEVT4 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
3	CEVT3	R/W	0h	FORCE CAPTURE EVENT 3:WRITING A 1 TO THIS BIT WILL SET THE CEVT3 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
2	CEVT2	R/W	0h	FORCE CAPTURE EVENT 2:WRITING A 1 TO THIS BIT WILL SET THE CEVT2 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
1	CEVT1	R/W	0h	FORCE CAPTURE EVENT 1:WRITING A 1 TO THIS BIT WILL SET THE CEVT1 FLAG BITWRITING OF 0 WILL BE IGNORED ALWAYS READS BACK A 0
0	_RESV0	R	0h