SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.6.2.9 ECAP_ECCTL2 Register

6.2.9.1 ECAP_ECCTL2 Register (Offset = 2Ah) [reset = 6h]

Capture Control Register 2

Table 3-478 Instance Table

Instance Name	Physical Address
ECAP0	5024 002Ah
ECAP1	5024 102Ah
ECAP2	5024 202Ah
ECAP3	5024 302Ah
ECAP4	5024 402Ah
ECAP5	5024 502Ah
ECAP6	5024 602Ah
ECAP7	5024 702Ah
ECAP8	5024 802Ah
ECAP9	5024 902Ah

Figure 3-231 ECAP_ECCTL2 Name Register

15	14	13	12	11	10	9	8
MODCNTRSTS		DMAEVTSEL		CTRFILTRESET	APWMPOL	CAP_APWM	SWSYNC
R/W		R/W		R/W1TC	R/W	R/W	R/W1TS
0h		0h		0h	0h	0h	0h
7	6	5	4	3	2	1	0
SYNCO_SEL		SYNCI_EN	TSCTRSTOP	REARM	STOP_WRAP		CONT_ONESHT
R/W		R/W	R/W	R/W1TS	R/W		R/W
0h		0h	0h	0h	3h		0h

Table 3-479 ECAP_ECCTL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:14	MODCNTRSTS	R/W	0h	This bit field reads current status on modulo counter 00b[R] = CAP1 register gets loaded on next capture event. 01b[R] = CAP2 register gets loaded on next capture event. 10b[R] = CAP3 register gets loaded on next capture event. 11b[R] = CAP4 register gets loaded on next capture event.
13:12	DMAEVTSEL	R/W	0h	DMA event select Capture Mode: 00b[R/W] = DMA interrupt source is CEVT1 01b[R/W] = DMA interrupt source is CEVT2 10b[R/W] = DMA interrupt source is CEVT3 11b[R/W] = DMA interrupt source is CEVT4 APWM Mode: 00b[R/W] = DMA interrupt source is period match 01b[R/W] = DMA interrupt source is compare match 10b[R/W] = DMA interrupt source is period match or compare match 11b[R/W] = Disabled
11	CTRFILTRESET	R/W1TC	0h	Reset Bit 0h[R] = No effect 1h[W] = Resets event filter, counter, modulo counter and CEVT[1,2,3,4] and CNTOVF , HRERROR flags Note: This provides an ability start capture module from known state in case spurious inputs are captured while ECAP is configured.
10	APWMPOL	R/W	0h	APWM output polarity select. This is applicable only in APWM operating mode. 1 Output is active low (Compare value defines low time) 0 Output is active high (Compare value defines high time)
9	CAP_APWM	R/W	0h	CAP/APWM operating mode select 1 ECAP module operates in APWM mode. This mode forces the following configuration: - Resets TSCTR on CTR = PRD event (period boundary ) - Permits shadow loading on CAP1 and 2 registers - Disables loading of time-stamps into CAP1-4 registers - CAPx/APWMx pin operates as a APWM output 0 ECAP module operates in capture mode. This mode forces the following configuration: - Inhibits TSCTR resets via CTR = PRD event - Inhibits shadow loads on CAP1 and 2 registers - Permits user to enable CAP1-4 register load - CAPx/APWMx pin operates as a capture input
8	SWSYNC	R/W1TS	0h	Software-forced Counter [TSCTR] Synchronizer. This provides the user a method to generate a synchronization pulse through software. In APWM mode, the synchronization pulse can also be sourced from the CTR = PRD event. 1 Writing a one forces a TSCTR shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0,0. After writing a 1, this bit returns to a zero. Note: Selection CTR = PRD is meaningful only in APWM mode; however, you can choose it in CAP mode if you find doing so useful. 0 Writing a zero has no effect. Reading always returns a zero
7:6	SYNCO_SEL	R/W	0h	Sync-Out Select 3 Disable sync out signal 1 Select CTR = PRD event to be the sync-out signal 0 sync out signal is SWSYNC
5	SYNCI_EN	R/W	0h	Counter [TSCTR] Sync-In select mode 1 Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event. 0 Disable sync-in option
4	TSCTRSTOP	R/W	0h	Time Stamp [TSCTR] Counter Stop [freeze] Control 1 TSCTR free-running 0 TSCTR stopped
3	REARM	R/W1TS	0h	Re-Arming Control. Note: The re-arm function is valid in one shot or continuous mode 1 Arms the one-shot sequence as follows: (1) Resets the Mod4 counter to zero (2) Unfreezes the Mod4 counter (3) Enables capture register loads 0 Has no effect (reading always returns a 0)
2:1	STOP_WRAP	R/W	3h	Stop value for one-shot mode. This is the number [between 1-4] of captures allowed to occur before the CAP[1-4] registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number [between 1-4] of the capture register in which the circular buffer wraps around and starts again. Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions occur: - Mod4 counter is stopped [frozen] - Capture register loads are inhibited In one-shot mode, further interrupt events are blocked until re-armed. 3 Stop after Capture Event 4 in one-shot mode Wrap after Capture Event 4 in continuous mode. 2 Stop after Capture Event 3 in one-shot mode Wrap after Capture Event 3 in continuous mode. 1 Stop after Capture Event 2 in one-shot mode Wrap after Capture Event 2 in continuous mode. 0 Stop after Capture Event 1 in one-shot mode Wrap after Capture Event 1 in continuous mode.
0	CONT_ONESHT	R/W	0h	Continuous or one-shot mode control [applicable only in capture mode] 1 Operate in one-Shot mode 0 Operate in continuous mode