SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.51.1 ADC_CFG_ADCINTOVFCLR Register (Offset = Ch) [reset = 0h]

ADC Interrupt Overflow Clear Register.

Table 3-105 Instance Table

Figure 3-51 ADC_CFG_ADCINTOVFCLR Name Register

Table 3-106 ADC_CFG_ADCINTOVFCLR Register Field Descriptions

Bit	Field	Type	Reset	Description
15:4	RESERVED_1	R	0h	Reserved
3	ADCINT4	R/W1TS	0h	ADC Interrupt 4 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.
2	ADCINT3	R/W1TS	0h	ADC Interrupt 3 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.
1	ADCINT2	R/W1TS	0h	ADC Interrupt 2 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.
0	ADCINT1	R/W1TS	0h	ADC Interrupt 1 Overflow Clear Bits 0 No action. 1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set.