SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
R5SS Reset Cause Status register of corresponding R5SS.
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| Instance Name | Physical Address |
|---|---|
| MSS_RCM | 5320 8030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | R5SS1_RST_STATUS_CAUSE | ||||||
| NONE | R | ||||||
| 0h | 3h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| R5SS1_RST_STATUS_CAUSE | |||||||
| R | |||||||
| 3h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:11 | RESERVED | NONE | 0h | Reserved |
| 10:0 | R5SS1_RST_STATUS_CAUSE | R | 3h | Has the status because of which reset has happened. Bit0: POR Reset Bit1: Warm Reset [ALso set during POR Reset] Bit2: CR5SS1 STC Reset Bit3 Reset for CORE0 and MSS_CORE00_VIM using MSS_RCM::MSS_CR5SSA0_RST_CTRL Bit4: Reset for CORE1 and MSS_CORE10_VIM using MSS_RCM::MSS_CR5SSB0_RST_CTRL Bit5: Reset for CORE0 only using MSS_RCM::MSS_CORE00_RST_CTRL Bit6: Reset for CORE1 only using using MSS_RCM::MSS_CORE10_RST_CTRL Bit7: Reset for CORE0 and MSS_CORE00_VIM caused because of reset request by debugger in CORE00 Bit8: Reset for CORE10 and MSS_CORE10_VIM caused because of reset request by debugger in CORE10 Bit9: Reset for CR5SS0 by the RESET FSM using MSS_CTRL::R5SS0_CONTROL_RESET_FSM_TRIGGER Bit 10 : Reset for CR5SS1 using MSS_RCM.MSS_CR5SS_POR_RST_CTRL0 |