SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
CRC interrupt status register. Contains interrupt flags for different types of interrupt.
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| Instance Name | Physical Address |
|---|---|
| MCRC0 | 3500 0028h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED5 | CH4_TIMEOUT | CH4_UNDER | CH4_OVER | CH4_CRCFAIL | RESERVED4 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED4 | CH3_TIMEOUT | CH3_UNDER | CH3_OVER | CH3_CRCFAIL | RESERVED3 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED3 | CH2_TIMEOUT | CH2_UNDER | CH2_OVER | CH2_CRCFAIL | RESERVED2 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED2 | CH1_TIMEOUT | CH1_UNDER | CH1_OVER | CH1_CRCFAIL | RESERVED1 | ||
| R | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED5 | R | 0h | |
| 28 | CH4_TIMEOUT | R/W | 0h | Channel 4 CRC Timeout Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 27 | CH4_UNDER | R/W | 0h | Channel 4 CRC Underrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 26 | CH4_OVER | R/W | 0h | Channel 4 CRC Overrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 25 | CH4_CRCFAIL | R/W | 0h | Channel 4 CRC Compare Fail Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 24:21 | RESERVED4 | R | 0h | |
| 20 | CH3_TIMEOUT | R/W | 0h | Channel 3 CRC Timeout Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 19 | CH3_UNDER | R/W | 0h | Channel 3 CRC Underrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 18 | CH3_OVER | R/W | 0h | Channel 3 CRC Overrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 17 | CH3_CRCFAIL | R/W | 0h | Channel 3 CRC Compare Fail Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 16:13 | RESERVED3 | R | 0h | |
| 12 | CH2_TIMEOUT | R/W | 0h | Channel 2 CRC Timeout Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 11 | CH2_UNDER | R/W | 0h | Channel 2 CRC Underrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 10 | CH2_OVER | R/W | 0h | Channel 2 CRC Overrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 9 | CH2_CRCFAIL | R/W | 0h | Channel 2 CRC Compare Fail Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 8:5 | RESERVED2 | R | 0h | |
| 4 | CH1_TIMEOUT | R/W | 0h | Channel 1 CRC Timeout Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
| 3 | CH1_UNDER | R/W | 0h | Channel 1 CRC Underrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
| 2 | CH1_OVER | R/W | 0h | Channel 1 CRC Overrun Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
| 1 | CH1_CRCFAIL | R/W | 0h | Channel 1 CRC Compare Fail Status Flag. This bit is cleared by Writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
| 0 | RESERVED1 | R | 0h |