SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

2.2.57.1 ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_REG0 Register (Offset = 300h) [reset = 0h]

Enable Register 0

Table 4-535 Instance Table

Instance Name	Physical Address
ICSSM0	4802 0300h

Figure 4-251 ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_REG0 Name Register

Table 4-536 ICSSM_PR1_ICSS_INTC_INTC_SLV_ENABLE_REG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	ENABLE_31	W1TS	0h	Enable (set) for intr_in[31]
30	ENABLE_30	W1TS	0h	Enable (set) for intr_in[30]
29	ENABLE_29	W1TS	0h	Enable (set) for intr_in[29]
28	ENABLE_28	W1TS	0h	Enable (set) for intr_in[28]
27	ENABLE_27	W1TS	0h	Enable (set) for intr_in[27]
26	ENABLE_26	W1TS	0h	Enable (set) for intr_in[26]
25	ENABLE_25	W1TS	0h	Enable (set) for intr_in[25]
24	ENABLE_24	W1TS	0h	Enable (set) for intr_in[24]
23	ENABLE_23	W1TS	0h	Enable (set) for intr_in[23]
22	ENABLE_22	W1TS	0h	Enable (set) for intr_in[22]
21	ENABLE_21	W1TS	0h	Enable (set) for intr_in[21]
20	ENABLE_20	W1TS	0h	Enable (set) for intr_in[20]
19	ENABLE_19	W1TS	0h	Enable (set) for intr_in[19]
18	ENABLE_18	W1TS	0h	Enable (set) for intr_in[18]
17	ENABLE_17	W1TS	0h	Enable (set) for intr_in[17]
16	ENABLE_16	W1TS	0h	Enable (set) for intr_in[16]
15	ENABLE_15	W1TS	0h	Enable (set) for intr_in[15]
14	ENABLE_14	W1TS	0h	Enable (set) for intr_in[14]
13	ENABLE_13	W1TS	0h	Enable (set) for intr_in[13]
12	ENABLE_12	W1TS	0h	Enable (set) for intr_in[12]
11	ENABLE_11	W1TS	0h	Enable (set) for intr_in[11]
10	ENABLE_10	W1TS	0h	Enable (set) for intr_in[10]
9	ENABLE_9	W1TS	0h	Enable (set) for intr_in[9]
8	ENABLE_8	W1TS	0h	Enable (set) for intr_in[8]
7	ENABLE_7	W1TS	0h	Enable (set) for intr_in[7]
6	ENABLE_6	W1TS	0h	Enable (set) for intr_in[6]
5	ENABLE_5	W1TS	0h	Enable (set) for intr_in[5]
4	ENABLE_4	W1TS	0h	Enable (set) for intr_in[4]
3	ENABLE_3	W1TS	0h	Enable (set) for intr_in[3]
2	ENABLE_2	W1TS	0h	Enable (set) for intr_in[2]
1	ENABLE_1	W1TS	0h	Enable (set) for intr_in[1]
0	ENABLE_0	W1TS	0h	Enable (set) for intr_in[0]