SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.10.2.3 I2C_ICSTR Register

10.2.3.1 I2C_ICSTR Register (Offset = 8h) [reset = 0h]

I2C Interrupt Status register

Table 5-1244 Instance Table

Instance Name	Physical Address
I2C0	5250 0008h
I2C1	5250 1008h
I2C2	5250 2008h
I2C3	5250 3008h

Figure 5-616 I2C_ICSTR Name Register

31	30	29	28	27	26	25	24
NU2
NU2
0h
23	22	21	20	19	18	17	16
NU2
NU2
0h
15	14	13	12	11	10	9	8
NU2	SDIR	NACKSNT	BB	RSFULL	XSMT	AAS	AD0
NU2	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
NU1		SCD	ICXRDY	ICRRDY	ARDY	NACK	AL
NU1		R/W	R/W	R/W	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h

Table 5-1245 I2C_ICSTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:15	NU2	NU2	0h	Reserved
14	SDIR	R/W	0h	Target Direction. This bit is clear to '0' indicating the I2C is a master transmitter/receiver or a target receiver. This bit is also clear by STOP condition or START condition. It is set to '1' when the I2C target is a transmitter. In DLB mode [which the configuration should be master-transmitter target-receiver] this bit is clear to '0'. Writing a"1" to this bit to clear it.
13	NACKSNT	R/W	0h	A No Acknowledge is sent due to NACKMOD is set to a"1". NACKSNT 0:A No Acknowledge is not sent. NACKSNT 1:A No Acknowledge is sent. Writing a"1" to this bit to clear it.
12	BB	R/W	0h	Bus Busy. This bit indicates the state of the serial bus. BB 0:The bus is free. BB 1:The bus is occupied. On reception of a"start" condition the device sets BB to 1. This bit is also set if the I2C detects SCL low state. BB is clear to 0 after reception of a"stop" condition. BB is kept to"0" regardless SCL state when the I2C is in reset [IRS_=0]. If the IRS_ is set to"1" during transaction between other I2C devices the BB bit is set at the first falling edge of SCL or START condition. - [RW ]
11	RSFULL	R/W	0h	Receive shift full. This bit indicates whether the receiver has experienced overrun. Overrun occurs when the receive shift register [ICRSR] is full and ICDRR has not been read since the ICRSR-to-ICDRR transfer. The FSM is holding for ICDRR read access. RSFULL is clear when Reading the ICDRR. RSFULL is set to"1" when the I2C has recognized an overrun. The contents of ICDRR are NOT lost in this case. In repeat mode since double buffer [ICRSR and ICDRR] behaves like a single buffer RSFULL is set to"1" every time the data is received. RSFULL is clear as a result of Reading the ICDRR. - [RW ]
10	XSMT	R/W	0h	Transmit shift empty not. This bit indicates whether the transmitter has experienced underflow. Underflow occurs when the transmit shift register [ICXSR] is empty and ICDXR has not been loaded. The FSM is holding for ICDXR write access. XSMT_ is cleared when underflow has occurred. XSMT_ is set to"1" as a result of Writing to ICDXR. In repeat mode if the I2C in master transmitter mode is holding transfer with XSMT_=0 [i.e. waiting for further action] and the STT or STP bit is set XSMT_ is set to"1" by hardware.
9	AAS	R/W	0h	Address As Target. This bit is set to 1 by the device when it has recognized its own target address or an address of all [8] zeros. The AAS bit is reset by stop condition or detection of any address byte that does not match ICOAR. - [RW ]
8	AD0	R/W	0h	Address Zero Status: This bit is set to 1 by device if it detects the address of all [8] zeros [i.e. general call]. The AD0 bit is reset to 0 [default value] when a"start" or"stop" condition is detected. - [RW ]
7:6	NU1	NU1	0h	Reserved
5	SCD	R/W	0h	Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition. This bit is cleared by Reading ICIVR [as 110] or Writing '1' to itself.
4	ICXRDY	R/W	0h	Transmit Data Ready interrupt flag bit. ICXRDY is set to"1" is generated when the transmitted data has been copied from ICDXR to the transmit-shift register [ICXSR]. ICRXDY is clear to"0" when the ICDXR is written. This bit can also be polled by the CPU to write a new transmitted data into the ICDXR. Write '1' to this bit will set it and DXR Write will clear it.
3	ICRRDY	R/W	0h	Receive Data Ready interrupt flag bit. ICRRDY is set to"1" when the received data has been copied from ICRSR into the ICDRR. ICRRDY is cleared to"0" when the ICDRR is read. This bit can also be polled by the CPU to read the received data in the ICDRR. Write '1' or DRR Read will clear it.
2	ARDY	R/W	0h	Register-access-ready interrupt flag bit. ARDY is generated by the hardware if the I2C is in the master mode when the previously programmed data and command has been performed and status bit has been updated. This flag is used by the CPU to let it knows that the I2C registers are ready to be accessed again. When RM=0 ARDY is set when the internal data count is passed 0 if STP register bit has not been set. When RM=1 ARDY is set at each byte end. If the I2C is in FDF mode[FDF=1] ARDY is set just after Start condition. This bit is automatically cleared by hardware when Writing data to ICDXR in transmit mode Reading data from ICDRR in receive mode or setting STT or STP bit. Write '1' will clear it.
1	NACK	R/W	0h	No-Acknowledgement interrupt flag bit. The No Acknowledge flag bit is set when the hardware in "master" mode detects no acknowledge has been received. This bit is NOT set by no-acknowledgement after Start byte Write '1' or Read the ICIVR [as 010] will clear it.
0	AL	R/W	0h	Arbitration-Lost interrupt flag bit. The Arbitration Lost flag bit is set to 1 when the device in the "master" mode senses it has lost an arbitration when two or more transmitters start a transmission almost simultaneously or when the I2C attempts to start a transfer while BB [bus busy] is 1. When this is set to 1 due to arbitration lost the MST/STT/STP bits are clear the I2C becomes a target. Write '1' or Read the ICIVR [as 001] will clear it.