SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.11.2.7 LIN_SCICLEARINTLVL Register

11.2.7.1 LIN_SCICLEARINTLVL Register (Offset = 18h) [reset = 0h]

The SCICLEARINTLVL register is used to map individual interrupt sources to the INT0 line.

Table 5-1304 Instance Table

Instance Name	Physical Address
LIN0	5240 0018h
LIN1	5240 1018h
LIN2	5240 2018h
LIN3	5240 3018h
LIN4	5240 4018h

Figure 5-645 LIN_SCICLEARINTLVL Name Register

31	30	29	28	27	26	25	24
CLRBEINTLVL	CLRPBEINTLVL	CLRCEINTLVL	CLRISFEINTLVL	CLRNREINTLVL	CLRFEINTLVL	CLROEINTLVL	CLRPEINTLVL
R/W1TC	R/W1TC	R/W1TC	R/W1TC	R/W1TC	R/W1TC	R/W1TC	R/W1TC
0h	0h	0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
RESERVED_7					RESERVED_6	RESERVED_5
R					R	R
0h					0h	0h
15	14	13	12	11	10	9	8
RESERVED_4		CLRIDINTLVL	RESERVED_3			CLRRXINTLVL	CLRTXINTLVL
R		R/W1TC	R			R/W1TC	R/W1TC
0h		0h	0h			0h	0h
7	6	5	4	3	2	1	0
CLRTOA3WUSINTLVL	CLRTOAWUSINTLVL	RESERVED_2	CLRTIMEOUTINTLVL	RESERVED_1		CLRWAKEUPINTLVL	CLRBRKDTINTLVL
R/W1TC	R/W1TC	R	R/W1TC	R		R/W1TC	R/W1TC
0h	0h	0h	0h	0h		0h	0h

Table 5-1305 LIN_SCICLEARINTLVL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	CLRBEINTLVL	R/W1TC	0h	Clear Bit Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Bit Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
30	CLRPBEINTLVL	R/W1TC	0h	Clear Physical Bus Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Physical Bus Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
29	CLRCEINTLVL	R/W1TC	0h	Clear Checksum-error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Checksum-error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
28	CLRISFEINTLVL	R/W1TC	0h	Clear Inconsistent-Sync-Field-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the Inconsistent-Sync-Field-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
27	CLRNREINTLVL	R/W1TC	0h	Clear No-Reponse-Error interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the No-Response-Error interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
26	CLRFEINTLVL	R/W1TC	0h	Clear Framing-Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Framing-Error interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
25	CLROEINTLVL	R/W1TC	0h	Clear Overrun-Error Interrupt Level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Overrun-Error interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
24	CLRPEINTLVL	R/W1TC	0h	Clear Parity Error interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Parity Error interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
23:19	RESERVED_7	R	0h	Reserved
18	RESERVED_6	R	0h	Reserved
17:16	RESERVED_5	R	0h	Reserved
15:14	RESERVED_4	R	0h	Reserved
13	CLRIDINTLVL	R/W1TC	0h	Clear ID interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the ID interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
12:10	RESERVED_3	R	0h	Reserved
9	CLRRXINTLVL	R/W1TC	0h	Clear Receiver interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the receiver interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
8	CLRTXINTLVL	R/W1TC	0h	Clear Transmitter interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the transmitter interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
7	CLRTOA3WUSINTLVL	R/W1TC	0h	Clear Timeout After 3 Wakeup Signals interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout after 3 wakeup signals interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
6	CLRTOAWUSINTLVL	R/W1TC	0h	Clear Timeout After Wakeup Signal interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the the timeout after wakeup interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
5	RESERVED_2	R	0h	Reserved
4	CLRTIMEOUTINTLVL	R/W1TC	0h	Clear Timeout interrupt level. This bit is effective in LIN mode only. Writing to this bit maps the timeout interrupt level to the INT0 line. This field is writable in LIN mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.
3:2	RESERVED_1	R	0h	Reserved
1	CLRWAKEUPINTLVL	R/W1TC	0h	Clear Wake-up interrupt level. This bit is effective in LIN or SCI-compatible mode. Writing to this bit maps the Wake-up interrupt level to the INT0 line. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line. Writing a 0 to this bit has no effect.
0	CLRBRKDTINTLVL	R/W1TC	0h	Clear Break-detect interrupt level. This bit is effective in SCI-compatible mode only. Writing to this bit maps the Break-detect interrupt level to the INT0 line. This field is writable in SCI mode only. 1 Interrupt level mapped to INT1 line. Writing a 1 to this bit will map the interrupt to INT0 and clear this bit. 0 Interrupt level mapped to INT0 line.