SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Configuration Register
This register is used:
- to select the functional mode or the SYSTEST mode for any card.
- to send an initialization sequence to any card.
- to enable the detection on DAT[1] of a card interrupt for SDIO cards only.
and also to configure :
- specific data and command transfers for MMC cards only.
- the parameters related to the card detect and write protect input signals.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 4830 012Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SDMA_LNE | DMA_MNS | DDR | BOOT_CF0 | BOOT_ACK | CLKEXTFREE | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PADEN | OBIE | OBIP | CEATA | CTPL | DVAL | WPP | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 3h | 0h | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CDP | MIT | DW8 | MODE | STR | HR | INIT | OD |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:22 | RESERVED | R | 0h | |
| 21 | SDMA_LNE | R/W | 0h | Target DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCSD_DATA register or late de-assertion, request remains active until last allowed data written into MMCSD_DATA. 1 Slave DMA level sensitive, Late DMA de-
assertion
0 Slave DMA edge sensitive, Early DMA de-
assertion |
| 20 | DMA_MNS | R/W | 0h | DMA Master or Target selection: When this bit is set and the controller is configured to use the DMA, Ocp master interface is used to get datas from system using ADMA2 procedure [direct access to the memory].This option is only available if generic parameter MADMA_EN is asserted to '1'. 1 The controller is master on data exchange
with system, controller must be configured
as using DMA.
0 The controller is slave on data transfers
with system. |
| 19 | DDR | R/W | 0h | Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCSD_SYSCTL[CLKD], it is insensitive to MMCSD_HCTL[HSPE] setting. 1 Data Bytes and CRC are transmitted on both
edge.
0 Standard mode : data are transmitted on a
single edge depending on MMCHS_HCTRL[HSPE]. |
| 18 | BOOT_CF0 | R/W | 0h | Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after Writing in MMCSD_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction. 1 CMD line forced to '0' is enabled and will
be active after writing into MMCHS_CMD
1 CMD line forced to '0' is enabled
0 CMD line is released when it was previously
forced to '0' by a boot sequence.
0 CMD line not forced |
| 17 | BOOT_ACK | R/W | 0h | Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated. 1 A boot status will be received on DAT0 line
after issuing a command.
0 No acknowledge to be received |
| 16 | CLKEXTFREE | R/W | 0h | External clock free running: This register is used to maintain card clock out of transfer transaction to enable target module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCSD_SYSCTL[CEN] is set. 1 External card clock is maintain even out of
active transaction period only if
MMCHS_SYSCTL[CEN] is set.
0 External card clock is cut off outside
active transaction period. |
| 15 | PADEN | R/W | 0h | Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCSD_CON[CTPL] bit. 1 ADPIDLE module pin is forced to active
state.
0 ADPIDLE module pin is not forced, it is
automatically generated by the MMC fsms. |
| 14 | OBIE | R/W | 0h | Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal [OBI] is optional and depends on the system integration. 1 Out-of-Band interrupt detection enabled 0 Out-of-Band interrupt detection disabled |
| 13 | OBIP | R/W | 0h | Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal [OBI] is optional and depends on the system integration. 1 Active low level 0 Active high level |
| 12 | CEATA | R/W | 0h | CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features. 1 CE-ATA mode next commands are considered as
CE-ATA commands.
0 Standard MMC/SD/SDIO mode. |
| 11 | CTPL | R/W | 0h | Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers. 1 Disable all the input buffers except the
buffer of DAT[1] outside of a transaction.
0 Disable all the input buffers outside of a
transaction. |
| 10:9 | DVAL | R/W | 3h | Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal [SDCD]. The usage of the card detect input signal [SDCD] is optional and depends on the system integration and the type of the connector housing that accommodates the card. 3 8,4 ms debounce period 2 1 ms debounce period 1 231 us debounce period 0 33 us debounce period |
| 8 | WPP | R/W | 0h | Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal [SDWP]. The usage of the write protect input signal [SDWP] is optional and depends on the system integration and the type of the connector housing that accommodates the card. 1 Active low level 0 Active high level |
| 7 | CDP | R/W | 0h | Card detect polarity All cards This bit selects the active level of the card detect input signal [SDCD]. The usage of the card detect input signal [SDCD] is optional and depends on the system integration and the type of the connector housing that accommodates the card. 1 Active high level 0 Active low level |
| 6 | MIT | R/W | 0h | MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register [MMCSD_CMD] is for Writing a MMC interrupt command [CMD40] requiring the command timeout detection to be disabled for the command response. 1 Command timeout disabled 0 Command timeout enabled |
| 5 | DW8 | R/W | 0h | 8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command [CMD6] with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register [CSD and EXT_CSD] must be verified for compliancy with MMC standard specification 4.x [see section 3.6]. 1 8-bit Data width (DAT[7:0] used, MMC cards)
0 1-bit or 4-bit Data width (DAT[0] used,
MMC, SD cards) |
| 4 | MODE | R/W | 0h | Mode select All cards These bits select between Functional mode and SYSTEST mode. 1 SYSTEST mode The signal pins are
configured as general-purpose input/output
and the 1024-byte buffer is configured as a
stack memory accessible only by the local
host or system DMA. The pins retain their
default type (input, output or in-out).
SYSTEST mode is operated under the control
of the SYSTEST register.
0 Functional mode. Transfers to the
MMC/SD/SDIO cards follow the card protocol.
MMC clock is enabled. MMC/SD transfers are
operated under the control of the CMD
register. |
| 3 | STR | R/W | 0h | Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers [read or write] of the adtc commands. Stream read is a class 1 command [CMD11: READ_DAT_UNTIL_STOP]. Stream write is a class 3 command [CMD20: WRITE_DAT_UNTIL_STOP]. 1 Stream oriented data transfer 0 Block oriented data transfer |
| 2 | HR | R/W | 0h | Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core [see section 4.3, "Interrupt Mode", in the MMC [1] specification]. In order to have the host response to be generated in open drain mode, the register MMCSD_CON[OD] must be set to 1. When MMCSD_CON[CEATA] is set to 1 and MMCSD_ARG set to 0x00000000 when Writing 0x00000000 into MMCSD_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1. 1 The host generates a 48-bit response
instead of a command or a command
completion signal disable token.
0 The host does not generate a 48-bit
response instead of a command. |
| 1 | INIT | R/W | 0h | Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider [MMCSD_SYSCTL[CLKD]] should be set to ensure that 80 clock periods are greater than 1ms. [see section 9.3, "Power-Up", in the MMC card specification [1], or section 6.4 in the SD card specification [2]]. Note: in this mode, there is no command sent to the card and no response is expected 1 The host sends an initialization sequence.
0 The host does not send an initialization
sequence. |
| 0 | OD | R/W | 0h | Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response [see Broadcast host response register MMCSD_CON[HR]] 1 Open Drain or Broadcast host response 0 No Open Drain |