SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.8.1 GPMC_CONFIG Register (Offset = 50h) [reset = A00h]

The configuration register allows global configuration of the GPMC .

Table 5-1182 Instance Table

Instance Name	Physical Address
GPMC0	4840 0050h

Figure 5-586 GPMC_CONFIG Name Register

Table 5-1183 GPMC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED_1	R	0h	Write 0's for future compatibility. Read returns 0
11	WAIT3PINPOLARITY	R/W	1h	Selects the polarity of input pin WAIT3 1 WAIT3 active high 0 WAIT3 active low
10	WAIT2PINPOLARITY	R/W	0h	Selects the polarity of input pin WAIT2 1 WAIT2 active high 0 WAIT2 active low
9	WAIT1PINPOLARITY	R/W	1h	Selects the polarity of input pin WAIT1 1 WAIT1 active high 0 WAIT1 active low
8	WAIT0PINPOLARITY	R/W	0h	Selects the polarity of input pin WAIT0 1 WAIT0 active high 0 WAIT0 active low
7:5	RESERVED_0	R	0h	Write 0's for future compatibility. Read returns 0
4	WRITEPROTECT	R/W	0h	Controls the WP output pin level 1 WP output pin is high 0 WP output pin is low
3:2	RESERVED_2	R	0h	Write 0's for future compatibility. Read returns 0
1	LIMITEDADDRESS	R/W	0h	Limited Address device support 1 A26-A11 are not modified during an external memory access. 0 No effect
0	NANDFORCEPOSTEDWRITE	R/W	0h	Enables the Force Posted Write feature to NAND Cmd/Add/Data location 1 Enables Force Posted Write 0 Disables Force Posted Write