SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
ECC Error Status1 Register.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MCAN0 | 5270 0020h |
| MCAN1 | 5270 1020h |
| MCAN2 | 5270 2020h |
| MCAN3 | 5270 3020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ECC_BIT1_STS | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ECC_BIT1_STS | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CLR_ECC_CTRL_REG | CLR_ECC_PAR | CLR_ECC_OTHER | CLR_ECC_DED | CLR_ECC_SEC | |||
| W | W | W | W | W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ECC_CTRL_REG | ECC_PAR | ECC_OTHER | ECC_DED | ECC_SEC | |||
| W | W | W | W | W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | ECC_BIT1_STS | R | 0h | TI Internal : Data bit that corresponds to the single-bit error |
| 15 | CLR_ECC_CTRL_REG | W | 0h | TI Internal : Clear Ctrl Reg Error Status. Write 1 to clear. This bit is self clearing. |
| 14:13 | CLR_ECC_PAR | W | 0h | TI Internal : Clear Parity Error Status. Write 1 to clear. This bit is self clearing. |
| 12 | CLR_ECC_OTHER | W | 0h | TI Internal : Clear Other Error Status. Write 1 to clear. This bit is self clearing. |
| 11:10 | CLR_ECC_DED | W | 0h | TI Internal : Clear Double Bit Error Status. Write 1 to clear. This bit is self clearing. |
| 9:8 | CLR_ECC_SEC | W | 0h | TI Internal : Clear Single Bit Error Status. Write 1 to clear. This bit is self clearing. |
| 7 | ECC_CTRL_REG | W | 0h | TI Internal : Force ctrl reg pending interrupt. Write 1 to set. This bit is self clearing. |
| 6:5 | ECC_PAR | W | 0h | TI Internal : Force ECC parity pending interrupt. Write 1 to set. This bit is self clearing. |
| 4 | ECC_OTHER | W | 0h | TI Internal : Force ECC other pending interrupt. Write 1 to set. This bit is self clearing. |
| 3:2 | ECC_DED | W | 0h | TI Internal : Force ECC DED pending interrupt. Write 1 to set. This bit is self clearing. |
| 1:0 | ECC_SEC | W | 0h | TI Internal : Force ECC SEC pending interrupt. Write 1 to set. This bit is self clearing. |