SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.14.2.2 MCSPI_HL_HWINFO Register

14.2.2.1 MCSPI_HL_HWINFO Register (Offset = 4h) [reset = 9h]

Information about the IP module's hardware configuration, i.e. typically the module's HDL generics (if any).
Actual field format and encoding is up to the module's designer to decide.

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Table 5-1699 Instance Table

Instance Name	Physical Address
MCSPI0	5220 0004h
MCSPI1	5220 1004h
MCSPI2	5220 2004h
MCSPI3	5220 3004h
MCSPI4	5220 4004h

Figure 5-838 MCSPI_HL_HWINFO Name Register

31	30	29	28	27	26	25	24
RSVD
R
0h
23	22	21	20	19	18	17	16
RSVD
R
0h
15	14	13	12	11	10	9	8
RSVD
R
0h
7	6	5	4	3	2	1	0
RSVD	RETMODE	FFNBYTE					USEFIFO
R	R	R					R
0h	0h	4h					1h

Table 5-1700 MCSPI_HL_HWINFO Register Field Descriptions

Bit	Field	Type	Reset	Description
31:7	RSVD	R	0h	Reserved These bits are initialized to zero, and writes to them are ignored
6	RETMODE	R	0h	This bit field indicates whether the retention mode is supported using the pin PIRFFRET 1 Retention mode enabled 0 Retention mode disabled
5:1	FFNBYTE	R	4h	FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account 10 FIFO 256 bytes depth 8 FIFO 128 bytes depth 4 FIFO 64 bytes depth 2 FIFO 32 bytes depth 1 FIFO 16 bytes depth
0	USEFIFO	R	1h	Use of a FIFO enable: This bit field indicates if a FIFO is integrated within controller design with its management 1 FIFO and its management implemented in design with depth defined by FFNBYTE generic 0 FIFO not implemented in design