SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.9.2.3 GPMC_IRQSTATUS Register

9.2.3.1 GPMC_IRQSTATUS Register (Offset = 18h) [reset = 0h]

This interrupt status register regroups all the status of the module internal events that can generate an interrupt.

Table 5-1172 Instance Table

Instance Name	Physical Address
GPMC0	4840 0018h

Figure 5-581 GPMC_IRQSTATUS Name Register

31	30	29	28	27	26	25	24
RESERVED_218
R
0h
23	22	21	20	19	18	17	16
RESERVED_218
R
0h
15	14	13	12	11	10	9	8
RESERVED_218				WAIT3EDGEDETECTIONSTATUS	WAIT2EDGEDETECTIONSTATUS	WAIT1EDGEDETECTIONSTATUS	WAIT0EDGEDETECTIONSTATUS
R				R/W1TC	R/W1TC	R/W1TC	R/W1TC
0h				0h	0h	0h	0h
7	6	5	4	3	2	1	0
RESERVED_219						TERMINALCOUNTSTATUS	FIFOEVENTSTATUS
R						R/W1TC	R/W1TC
0h						0h	0h

Table 5-1173 GPMC_IRQSTATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED_218	R	0h	Write 0's for future compatibility. Read returns 0
11	WAIT3EDGEDETECTIONSTATUS	R/W1TC	0h	Status of the Wait3 Edge Detection interrupt 1 Read 1: A transition on WAIT3 input pin has been detected 1 Write 1: Wait3EdgeDetection status bit is reset 0 Read 0: A transition on WAIT3 input pin has not been detected 0 Write 0: Wait3EdgeDetection status bit unchanged
10	WAIT2EDGEDETECTIONSTATUS	R/W1TC	0h	Status of the Wait2 Edge Detection interrupt 1 Read 1: A transition on WAIT2 input pin has been detected 1 Write 1: Wait2EdgeDetection status bit is reset 0 Read 0: A transition on WAIT2 input pin has not been detected 0 Write 0: Wait2EdgeDetection status bit unchanged
9	WAIT1EDGEDETECTIONSTATUS	R/W1TC	0h	Status of the Wait1 Edge Detection interrupt 1 Read 1: A transition on WAIT1 input pin has been detected 1 Write 1: Wait1EdgeDetection status bit is reset 0 Read 0: A transition on WAIT1 input pin has not been detected 0 Write 0: Wait1EdgeDetection status bit unchanged
8	WAIT0EDGEDETECTIONSTATUS	R/W1TC	0h	Status of the Wait0 Edge Detection interrupt 1 Read 1: A transition on WAIT0 input pin has been detected 1 Write 1: Wait0EdgeDetection status bit is reset 0 Read 0: A transition on WAIT0 input pin has not been detected 0 Write 0: Wait0EdgeDetection status bit unchanged
7:2	RESERVED_219	R	0h	Write 0's for future compatibility. Read returns 0
1	TERMINALCOUNTSTATUS	R/W1TC	0h	Status of the TerminalCountEvent interrupt 1 Read 1: Indicates that CountValue is equal to 0 1 Write 1: TerminalCountEvent status bit is reset 0 Read 0: Indicates that CountValue is greater than 0 0 Write 0: TerminalCountEvent status bit unchanged
0	FIFOEVENTSTATUS	R/W1TC	0h	Status of the FIFOEvent interrupt 1 Read 1: Indicates than at least FIFOThreshold bytes are available in prefetch mode and at least FIFOThreshold bytes free places are available in write posting mode. 1 Write 1: FIFOEvent status bit is reset 0 Read 0: Indicates than less than FIFOThreshold bytes are available in prefetch mode and less than FIFOThreshold bytes free places are available in write posting mode. 0 Write 0: FIFOEvent status bit unchanged