SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.2.25.1 TOP_CTRL_TSENSE_CFG Register (Offset = D00h) [reset = 11110000h]

This register is used to enable and configure the Temperature sensors present in the device.

Table 2-978 Instance Table

Instance Name	Physical Address
TOP_CTRL	50D8 0D00h

Figure 2-488 TOP_CTRL_TSENSE_CFG Name Register

Table 2-979 TOP_CTRL_TSENSE_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:29	RESERVED	NONE	0h	Reserved
28	TSENSE_CFG_TMPSOFF	R/W	1h	Temperature sensor off 0 : on 1 : off **Note: This bit will only be reset by PORz.
27:25	RESERVED	NONE	0h	Reserved
24	TSENSE_CFG_BGROFF	R/W	1h	BandGap on/off control 1 : off 0 : on **Note: This bit will only be reset by PORz.
23:21	RESERVED	NONE	0h	Reserved
20	TSENSE_CFG_AIPOFF	R/W	1h	1 : iddq mode select 0 : normal mode **Note: This bit will only be reset by PORz.
19:17	RESERVED	NONE	0h	Reserved
16	TSENSE_CFG_SNSR_MX_HIZ	R/W	1h	Sensor mux hiz control 0 : normal operation. Mux will select either one of the anlaog sensor 1 : mux will be high impedence **Note: This bit will only be reset by PORz.
15:14	RESERVED	NONE	0h	Reserved
13:8	TSENSE_CFG_DELAY	R/W	0h	Number of wait clock cycles between each TMPS Readout. Configure a Non zero value as delay value since configuring 0 is not allowed **Note: This bit will only be reset by PORz.
7:4	TSENSE_CFG_SENSOR_SEL	R/W	0h	Sensor Selection sensor enable bits for each sensor 0 : sensor disable 1 : sensor enable bit 3:temp_sensor3 bit 2:temp_sensor2 bit 1:temp_sensor1 bit 0:temp_sensor0 **Note: This bit will only be reset by PORz.
3:1	RESERVED	NONE	0h	Reserved
0	TSENSE_CFG_ENABLE	R/W	0h	Temperature controller enable **Note: This bit will only be reset by PORz.