SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.24.2.39 UART_SCR Register

24.2.39.1 UART_SCR Register (Offset = 40h) [reset = 0h]

Note: Bit 4 enables the wake-up interrupt, but this interrupt is not mapped into the IIR register. Therefore, when an interrupt occurs and there is no interrupt pending in the IIR register, the SSR[1] bit must be checked. To clear the wake-up interrupt, bit SCR[4] must be reset to 0.

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Table 5-2347 Instance Table

Instance Name	Physical Address
UART0	5230 0040h
UART1	5230 1040h
UART2	5230 2040h
UART3	5230 3040h
UART4	5230 4040h
UART5	5230 5040h

Figure 5-1154 UART_SCR Name Register

31	30	29	28	27	26	25	24
RESERVED_24
R
0h
23	22	21	20	19	18	17	16
RESERVED_24
R
0h
15	14	13	12	11	10	9	8
RESERVED_24
R
0h
7	6	5	4	3	2	1	0
RX_TRIG_GRANU1	TX_TRIG_GRANU1	DSR_IT	RX_CTS_DSR_WAKE_UP_ENABLE	TX_EMPTY_CTL_IT	DMA_MODE_2		DMA_MODE_CTL
R/W	R/W	R/W	R/W	R/W	R/W		R/W
0h	0h	0h	0h	0h	0h		0h

Table 5-2348 UART_SCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED_24	R	0h
7	RX_TRIG_GRANU1	R/W	0h	1 ENABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL. 0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER RX LEVEL.
6	TX_TRIG_GRANU1	R/W	0h	1 Enables the granularity of 1 for trigger TX level. 0 DISABLES THE GRANULARITY OF 1 FOR TRIGGER TX LEVEL.
5	DSR_IT	R/W	0h	1 ENABLES DSR* INTERRUPT. 0 DISABLES DSR* INTERRUPT.
4	RX_CTS_DSR_WAKE_UP_ENABLE	R/W	0h	1 Waits for a falling edge of pins RX, CTS* or DSR* to generate an interrupt 0 DISABLES THE WAKE UP INTERRUPT AND CLEARS SSR[1].
3	TX_EMPTY_CTL_IT	R/W	0h	1 THE THR INTERRUPT IS GENERATED WHEN TX FIFO AND TX SHIFT REGISTER ARE EMPTY. 0 Normal mode for THR interrupt (See UART mode interrupts table).
2:1	DMA_MODE_2	R/W	0h	Used to specify the DMA mode valid if SCR[0] = 1 3 DMA mode 3 (UART_nDMA_REQ[0] in TX) 2 DMA mode 2 (UART_nDMA_REQ[0] in RX) 1 DMA mode 1 (UART_nDMA_REQ[0] in TX, UART_nDMA_REQ[1] in RX) 0 DMA mode 0 (no DMA)
0	DMA_MODE_CTL	R/W	0h	1 The DMA_MODE is set with SCR[2:1] 0 The DMA_MODE is set with FCR[3]