| *1 |
SPRUJ42*1 |
March 2022 |
Initial Creation
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| - |
SPRUJ42 |
April 2022 |
Original Release
Added Read This First Content
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| A |
SPRUJ42A |
September 2022 |
Memory Map Updates:
- Core-specific Memory Maps added
Updates included for the following CTRLMMR Registers:
- TOP_CTRL
- MSS_CTRL
- MSS_IOMUX
- MSS_TOPRCM
- MSS_RCM
CONTROLSS_EPWM Register Descriptions Added
Updates included for the following CONTROLSS Registers:
- CONTROLSS_ADC*
- CONTROLSS_CMPSS*
- CONTROLSS_DAC
- CONTROLSS_ECAP
- CONTROLSS_EQEP
- CONTROLSS_FSI*
- CONTROLSS_GLOBAL_CTRL
- CONTROLSS_*XBAR
Updates included for the following SoC Registers
- MSS_GPIO
- MSS_LIN
- MSS_SPINLOCK
|
| B |
SPRUJ42B |
October 2022 |
Updates included for the following CTRLMMR Registers:
- TOP_CTRL
- MSS_CTRL
- MSS_IOMUX
- MSS_TOPRCM
- MSS_RCM
Updates included for the following CONTROLSS Registers:
- CONTROLSS_CMPSS*
- CONTROLSS_ECAP
- CONTROLSS_EQEP
- CONTROLSS_GLOBAL_CTRL
- CONTROLSS_*XBAR
Updates included for the following SoC Registers
- XBAR and INTR Registers
- MSS_*
|
| C |
SPRUJ42C |
December 2022 |
Updates in general register description layout applied across document. PRU-ICSS Registers Added CONTROLSS_EPWM Registers Added Updates included for the following CTRLMMR Registers:
- TOP_CTRL
- MSS_CTRL
- MSS_IOMUX
- MSS_TOPRCM
- MSS_RCM
Updates included for the following SoC Registers
- XBAR and INTR Registers
- MSS_*
|
| D |
SPRUJ42D |
December 2023 |
- Aligned register reset values in tables and images
- Update register names with nomenclature used in other register addendums
- Uncompressed instances and registers in EPWM.
- Removed "n" variable from register nomenclature from CMPSSA, CMPSSB, ECAP, EQEP, FSI_RX, FSI_TX, OTTOCAL, R5SS, DCC, MCAN, MCRC, RTI, UART, and SDFM
- Adding missing figures. ESM, GPIO, I2C, and INPUTXBAR still need missing figures added
- CPSW combined into one chapter
- TCM, TCMA, TCMB, CCMR, and STC moved into R5SS_Core chapter
- Combined TPTC and TPCC chapter into EDMA chapter
- Removed chapter CTRLMMR_CONTROLSS_GLOBAL_CTRL which was one page linking to another chapter
- MCAN chapters combined into one chapter
- Changed AGG to AGGR
- TSXBAR_INTR renamed to SoC_TIMESYNC_XBAR0
- SOC_TSXBAR_INTR chapter renamed to SoC_TIMESYNC_XBAR1 and moved to 3.24
- TOP PBIST renamed to PBIST with instance name of PBIST0
- CMPSS instances renamed to CMPSS12B. Names to align with CMPSSA in future revision
- Global Control Registers have register name changes from epwm to etpwm and cmpssb to cmpss*b0.
- Added GPMC, ELM, and WDT chapters
|
| E |
SPRUJ42E |
October 2024 |
- Added MPU_16 and MPU_8 chapters
- Added new section for Processor and Accelerator Registers
- Aligned CMPSSB register names with CMPSSA register names
- ADC_CFG and ADC_RESULT_REGS have been compacted into ADC
- Individual ADC registers have been compacted to reflect ADC0-4 with minimal duplicate registers
- Numerous CPSW registers compacted with offset formulas to reduce chapter size
- Appended TPCC and TPTC to EDMA register names to better differentiate the different IP blocks
- Top Level Register Name updates:
- RFSS_CORE to R5SS
- PRU-ICSS to ICSSM
- PRU_ICSS_XBAR_INTR to ICSSM_XBAR_INTR
- EDMA_TRIGGER_XBAR_INTROUTER to EDMA_TRIGXBAR_INTR
- ECC_AGG_TOP to ECC_AGGR
- MSS_LIN to LIN
- TOP_ESM to ESM
- Updated IP and instance names across large portions of the document
- Register name updates to align with software names applied across large portions of the document
- Organized SoC peripherals by alphabet like Control Subsystem
- Resolved document-wide issues with incorrect reset values and offsets
- Updated PBIST Registers Base Address from "0x5330 0200" to "0x5330 0000"
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