SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The SCICLEARINT register is used to disable the enabled interrupts without accessing the SCISETINT register.
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| Instance Name | Physical Address |
|---|---|
| LIN0 | 5240 0010h |
| LIN1 | 5240 1010h |
| LIN2 | 5240 2010h |
| LIN3 | 5240 3010h |
| LIN4 | 5240 4010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CLRBEINT | CLRPBEINT | CLRCEINT | CLRISFEINT | CLRNREINT | CLRFEINT | CLROEINT | CLRPEINT |
| R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC | R/W1TC |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_6 | RESERVED_5 | SETRXDMA | CLRTXDMA | ||||
| R | R | R/W1TC | R/W1TC | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_4 | CLRIDINT | RESERVED_3 | CLRRXINT | CLRTXINT | |||
| R | R/W1TC | R | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLRTOA3WUSINT | CLRTOAWUSINT | RESERVED_2 | CLRTIMEOUTINT | RESERVED_1 | CLRWAKEUPINT | CLRBRKDTINT | |
| R/W1TC | R/W1TC | R | R/W1TC | R | R/W1TC | R/W1TC | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | CLRBEINT | R/W1TC | 0h | Clear Bit Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the bit error interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 30 | CLRPBEINT | R/W1TC | 0h | Clear Physical Bus Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the physical-bus error interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 29 | CLRCEINT | R/W1TC | 0h | Clear checksum-error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the checksum-error interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 28 | CLRISFEINT | R/W1TC | 0h | Clear Inconsistent-Sync-Field-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the ISFE interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 27 | CLRNREINT | R/W1TC | 0h | Clear No-Reponse-Error Interrupt. This bit is effective in LIN mode only. Setting this bit disables the no-response error interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 26 | CLRFEINT | R/W1TC | 0h | Clear Framing-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables framing-error interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 25 | CLROEINT | R/W1TC | 0h | Clear Overrun-Error Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the overrun interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 24 | CLRPEINT | R/W1TC | 0h | Clear Parity Interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the parity error interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 23:19 | RESERVED_6 | R | 0h | Reserved |
| 18 | RESERVED_5 | R | 0h | Reserved |
| 17 | SETRXDMA | R/W1TC | 0h | Clear receiver DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receive DMA request. 1 Receiver DMA request is enabled. Writing a
1 to this bit will disable the DMA request
and clear this bit.
0 Receiver DMA request is disabled. Writing a
0 to this bit has no effect. |
| 16 | CLRTXDMA | R/W1TC | 0h | Clear transmit DMA. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmit DMA request. 1 Transmit DMA request is enabled. Writing a
1 to this bit will disable the DMA request
and clear this bit.
0 Transmit DMA request is disabled. Writing a
0 to this bit has no effect. |
| 15:14 | RESERVED_4 | R | 0h | Reserved |
| 13 | CLRIDINT | R/W1TC | 0h | Clear Identifier interrupt. This bit is effective in LIN mode only. Setting this bit disables the ID interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 12:10 | RESERVED_3 | R | 0h | Reserved |
| 9 | CLRRXINT | R/W1TC | 0h | Clear Receiver interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the receiver interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 8 | CLRTXINT | R/W1TC | 0h | Clear Transmitter interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the transmitter interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 7 | CLRTOA3WUSINT | R/W1TC | 0h | Clear Timeout After 3 Wakeup Signals interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after 3 wakeup signals interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 6 | CLRTOAWUSINT | R/W1TC | 0h | Clear Timeout After Wakeup Signal interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout after one wakeup signal interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 5 | RESERVED_2 | R | 0h | Reserved |
| 4 | CLRTIMEOUTINT | R/W1TC | 0h | Clear Timeout interrupt. This bit is effective in LIN mode only. Setting this bit disables the timeout [LIN bus idle] interrupt. This field is writable in LIN mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 3:2 | RESERVED_1 | R | 0h | Reserved |
| 1 | CLRWAKEUPINT | R/W1TC | 0h | Clear Wake-up interrupt. This bit is effective in LIN or SCI-compatible mode. Setting this bit disables the wake-up interrupt. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |
| 0 | CLRBRKDTINT | R/W1TC | 0h | Clear Break-detect interrupt. This bit is effective in SCI-compatible mode only. Setting this bit disables the Break-detect interrupt. This field is writable in SCI mode only. 1 Interrupt is enabled. Writing a 1 to this
bit will disable the interrupt and clear
this bit.
0 Interrupt is disabled. Writing a 0 to this
bit has no effect. |