SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.8.2.13 EQEP_QEPCTL Register

8.2.13.1 EQEP_QEPCTL Register (Offset = 2Ah) [reset = 0h]

QEP Control .

Return to Summary Table

Table 3-962 Instance Table

Instance Name	Physical Address
EQEP0	5027 002Ah
EQEP1	5027 102Ah
EQEP2	5027 202Ah

Figure 3-451 EQEP_QEPCTL Name Register

15	14	13	12	11	10	9	8
FREE_SOFT		PCRM		SEI		IEI
R/W		R/W		R/W		R/W
0h		0h		0h		0h
7	6	5	4	3	2	1	0
SWI	SEL	IEL		QPEN	QCLM	UTE	WDE
R/W	R/W	R/W		R/W	R/W	R/W	R/W
0h	0h	0h		0h	0h	0h	0h

Table 3-963 EQEP_QEPCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
15:14	FREE_SOFT	R/W	0h	Emulation mode 3 Same as FREE_SOFT_2 2 QPOSCNT behavior Position counter is unaffected by emulation suspend 2h (R/W) = QWDTMR behavior Watchdog counter is unaffected by emulation suspend 2h (R/W) = QUTMR behavior Unit timer is unaffected by emulation suspend 2h (R/W) = QCTMR behavior Capture Timer is unaffected by emulation suspend 1 QPOSCNT behavior Position counter continues to count until the rollover 1h (R/W) = QWDTMR behavior Watchdog counter counts until WD period match roll over 1h (R/W) = QUTMR behavior Unit timer counts until period rollover 1h (R/W) = QCTMR behavior Capture Timer counts until next unit period event 0 QPOSCNT behavior Position counter stops immediately on emulation suspend 0h (R/W) = QWDTMR behavior Watchdog counter stops immediately 0h (R/W) = QUTMR behavior Unit timer stops immediately 0h (R/W) = QCTMR behavior Capture Timer stops immediately
13:12	PCRM	R/W	0h	Postion counter reset 3 Position counter reset on a unit time event 2 Position counter reset on the first index event 1 Position counter reset on the maximum position 0 Position counter reset on an index event
11:10	SEI	R/W	0h	Strobe event initialization of position counter 3 Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe 2 Initializes the position counter on rising edge of the QEPS signal 1 Does nothing (action disabled) 0 Does nothing (action disabled)
9:8	IEI	R/W	0h	Index event init of position count 3 Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT) 2 Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 1 Do nothing (action disabled) 0 Do nothing (action disabled)
7	SWI	R/W	0h	Software init position counter 1 Initialize position counter (QPOSCNT=QPOSINIT). This bit is not cleared automatically 0 Do nothing (action disabled)
6	SEL	R/W	0h	Strobe event latch of position counter 1 Clockwise Direction: Position counter is latched on rising edge of QEPS strobe Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe 0 The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the QDECCTL register
5:4	IEL	R/W	0h	Index event latch of position counter [software index marker] 3 Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to the QPOSILAT register and the direction flag is latched in the QEPSTS[QDLF] bit. This mode is useful for software index marking. 2 Latches position counter on falling edge of the index signal 1 Latches position counter on rising edge of the index signal 0 Reserved
3	QPEN	R/W	0h	Quadrature position counter enable/software reset 1 eQEP position counter is enabled 0 Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. When QPEN is disabled, some flags in the QFLG register do not get reset or cleared and show the actual state of that flag.
2	QCLM	R/W	0h	QEP capture latch mode 1 Latch on unit time out. Position counter, capture timer and capture period values are latched into QPOSLAT, QCTMRLAT and QCPRDLAT registers on unit time out. 0 Latch on position counter read by CPU. Capture timer and capture period values are latched into QCTMRLAT and QCPRDLAT registers when CPU reads the QPOSCNT register.
1	UTE	R/W	0h	QEP unit timer enable 1 Enable unit timer 0 Disable eQEP unit timer
0	WDE	R/W	0h	QEP watchdog enable 1 Enable the eQEP watchdog timer 0 Disable the eQEP watchdog timer