SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

6.2.15.1 ECAP_HRCTL Register (Offset = 40h) [reset = 0h]

High-Res Control Register .

Table 3-490 Instance Table

Figure 3-237 ECAP_HRCTL Name Register

Table 3-491 ECAP_HRCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:6	RESERVED_1	R/W	0h	Reserved
5	CALIBCONT	R/W	0h	Continuous mode Calibration Select Bit: 0 Continuous mode disabled. 1 Continuous mode enabled. Calibration automatically restarts at end of current calibration cycle.
4	CALIBSTS	R	0h	Calibration status Bit: 0 No active calibration cycle 1 Calibration cycle in progress
3	CALIBSTART	R/W1TS	0h	Calibration start Bit: 0 No effect 1 Starts the calibration cycle
2	PRDSEL	R/W	0h	Calibration Period Match Select Bit: 0 Use SYSCLK Counter For Period Match [default at reset] 1 Reserved
1	HRCLKE	R/W	0h	High Resolution Clock Enable Bit: 0 High resolution clock disabled [default at reset] 1 High resolution clock enabled. The clock should be enabled before enabling the high res function via the HRE bit.
0	HRE	R/W	0h	High Resolution Enable Bit: 0 High resolution mode disabled [default at reset] 1 High resolution mode enabled. Enabling this mode will connect the capture registers and edge event modes of the ECAP to be accessed by the High Res function. Note: The High Res clock needs to be enabled [using the HRCLKE bit] first before enabling the module. Allow a certain start up stabilization period before enabling the module.