SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.24.2.18 UART_LSR_UART Register

24.2.18.1 UART_LSR_UART Register (Offset = 14h) [reset = 60h]

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Table 5-2305 Instance Table

Instance Name	Physical Address
UART0	5230 0014h
UART1	5230 1014h
UART2	5230 2014h
UART3	5230 3014h
UART4	5230 4014h
UART5	5230 5014h

Figure 5-1133 UART_LSR_UART Name Register

31	30	29	28	27	26	25	24
RESERVED_24
R
0h
23	22	21	20	19	18	17	16
RESERVED_24
R
0h
15	14	13	12	11	10	9	8
RESERVED_24
R
0h
7	6	5	4	3	2	1	0
RX_FIFO_STS	TX_SR_E	TX_FIFO_E	RX_BI	RX_FE	RX_PE	RX_OE	RX_FIFO_E
R	R	R	R	R	R	R	R
0h	1h	1h	0h	0h	0h	0h	0h

Table 5-2306 UART_LSR_UART Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED_24	R	0h
7	RX_FIFO_STS	R	0h	1 At least one parity error, framing error or break indication in the RX FIFO. Bit 7 is cleared when no more errors are present in the RX FIFO. 0 Normal operation
6	TX_SR_E	R	1h	1 Transmitter hold (TX FIFO) and shift registers are empty 0 Transmitter hold (TX FIFO) and shift registers are not empty.
5	TX_FIFO_E	R	1h	1 Transmit hold register (TX FIFO) is empty. The transmission is not necessarily completed. 0 Transmit hold register (TX FIFO) is not empty
4	RX_BI	R	0h	1 A break was detected while the data being read from the RX FIFO was being received. (i.e. RX input was low for one character + 1 bit time frame). 0 No break condition
3	RX_FE	R	0h	1 Framing error occurred in data being read from RX FIFO.(received data did not have a valid stop bit) 0 No framing error in data being read from RX FIFO.
2	RX_PE	R	0h	1 Parity error in data being read from RX FIFO 0 No parity error in data being read from RX FIFO.
1	RX_OE	R	0h	1 Overrun error has occurred. Set when the character held in the receive shift register is not transferred to the RX FIFO. This case can occurs only when receive FIFO is full. 0 No overrun error
0	RX_FIFO_E	R	0h	1 At least one data character in the RX FIFO 0 No data in the receive FIFO