SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The IIR is a read-only register, which provides the source of the interrupt in a prioritized manner.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 5230 0008h |
| UART1 | 5230 1008h |
| UART2 | 5230 2008h |
| UART3 | 5230 3008h |
| UART4 | 5230 4008h |
| UART5 | 5230 5008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FCR_MIRROR | IT_TYPE | IT_PENDING | |||||
| R | R | R | |||||
| 0h | 0h | 1h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7:6 | FCR_MIRROR | R | 0h | Mirror the contents of FCR[0] on both bits. |
| 5:1 | IT_TYPE | R | 0h | 16 CTS, RTS, DSR change state from active
(low) to inactive (high). Priority=6
8 Xoff/Special character. Priority=5
6 Rx timeout. Priority=2
3 Receiver line status error. Priority=3
2 RHR interrupt. Priority=2
1 THR interrupt. Priority=3
0 Modem Interrupt. Priority=4 |
| 0 | IT_PENDING | R | 1h | 1 No interrupt is pending 0 An interrupt is pending |