SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.14.2.7 MCSPI_IRQENABLE Register

14.2.7.1 MCSPI_IRQENABLE Register (Offset = 11Ch) [reset = 0h]

This register allows to enable/disable the module internal sources of interrupt, on an event-by-event basis.

Table 5-1709 Instance Table

Instance Name	Physical Address
MCSPI0	5220 011Ch
MCSPI1	5220 111Ch
MCSPI2	5220 211Ch
MCSPI3	5220 311Ch
MCSPI4	5220 411Ch

Figure 5-843 MCSPI_IRQENABLE Name Register

31	30	29	28	27	26	25	24
RESERVED_5
R
0h
23	22	21	20	19	18	17	16
RESERVED_5						EOW_ENABLE	WKE
R						R/W	R/W
0h						0h	0h
15	14	13	12	11	10	9	8
RESERVED_4	RX3_FULL_ENABLE	TX3_UNDERFLOW_ENABLE	TX3_EMPTY_ENABLE	RESERVED_6	RX2_FULL_ENABLE	TX2_UNDERFLOW_ENABLE	TX2_EMPTY_ENABLE
R	R/W	R/W	R/W	R	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
7	6	5	4	3	2	1	0
RESERVED_3	RX1_FULL_ENABLE	TX1_UNDERFLOW_ENABLE	TX1_EMPTY_ENABLE	RX0_OVERFLOW_ENABLE	RX0_FULL_ENABLE	TX0_UNDERFLOW_ENABLE	TX0_EMPTY_ENABLE
R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-1710 MCSPI_IRQENABLE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED_5	R	0h	Reads return 0
17	EOW_ENABLE	R/W	0h	End of Word count Interrupt Enable 1 Interrupt enabled 0 Interrupt disabled
16	WKE	R/W	0h	Wake Up event interrupt Enable in target mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV] 1 Interrupt enabled 0 Interrupt disabled
15	RESERVED_4	R	0h	Reads returns 0
14	RX3_FULL_ENABLE	R/W	0h	Receiver register Full Interrupt Enable Ch 3 1 Interrupt enabled 0 Interrupt disabled
13	TX3_UNDERFLOW_ENABLE	R/W	0h	Transmitter register Underflow Interrupt Enable Ch 3 1 Interrupt enabled 0 Interrupt disabled
12	TX3_EMPTY_ENABLE	R/W	0h	Transmitter register Empty Interrupt Enable Ch3 1 Interrupt enabled 0 Interrupt disabled
11	RESERVED_6	R	0h	Reads return 0
10	RX2_FULL_ENABLE	R/W	0h	Receiver register Full Interrupt Enable Ch 2 1 Interrupt enabled 0 Interrupt disabled
9	TX2_UNDERFLOW_ENABLE	R/W	0h	Transmitter register Underflow Interrupt Enable Ch 2 1 Interrupt enabled 0 Interrupt disabled
8	TX2_EMPTY_ENABLE	R/W	0h	Transmitter register Empty Interrupt Enable Ch 2 1 Interrupt enabled 0 Interrupt disabled
7	RESERVED_3	R	0h	Reads return 0
6	RX1_FULL_ENABLE	R/W	0h	Receiver register Full Interrupt Enable Ch 1 1 Interrupt enabled 0 Interrupt disabled
5	TX1_UNDERFLOW_ENABLE	R/W	0h	Transmitter register Underflow Interrupt Enable Ch 1 1 Interrupt enabled 0 Interrupt disabled
4	TX1_EMPTY_ENABLE	R/W	0h	Transmitter register Empty Interrupt Enable Ch 1 1 Interrupt enabled 0 Interrupt disabled
3	RX0_OVERFLOW_ENABLE	R/W	0h	Receiver register Overflow Interrupt Enable Ch 0 1 Interrupt enabled 0 Interrupt disabled
2	RX0_FULL_ENABLE	R/W	0h	Receiver register Full Interrupt Enable Ch 0 1 Interrupt enabled 0 Interrupt disabled
1	TX0_UNDERFLOW_ENABLE	R/W	0h	Transmitter register Underflow Interrupt Enable Ch 0 1 Interrupt enabled 0 Interrupt disabled
0	TX0_EMPTY_ENABLE	R/W	0h	Transmitter register Empty Interrupt Enable Ch 0 1 Interrupt enabled 0 Interrupt disabled