SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
The interrupt identification register (IIR) is a read-only register at the same address as the FIFO control register (FCR), which is a write-only register. When an interrupt is generated and enabled in the interrupt enable register (IER), IIR indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading IIR clears any THR empty (THRE) interrupts that are pending.
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| Instance Name | Physical Address |
|---|---|
| ICSSM0 | 4802 8008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ||
| W | NONE | W | W | W | W | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIFOEN | RESERVED | INTID | IPEND | ||||
| R | NONE | R | R | ||||
| 0h | 0h | 0h | 1h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:14 | RESERVED | W | 0h | Reserved |
| 13:12 | RESERVED | NONE | 0h | Reserved |
| 11 | RESERVED | W | 0h | Reserved |
| 10 | RESERVED | W | 0h | Reserved |
| 9 | RESERVED | W | 0h | Reserved |
| 8 | RESERVED | W | 0h | Reserved |
| 7:6 | FIFOEN | R | 0h | FIFOs enabled 3h FIFOs are enabled. FIFOEN bit in the FIFO
control register (FCR) is set to 1.
1h-2h Reserved
0h Non-FIFO mode |
| 5:4 | RESERVED | NONE | 0h | Reserved |
| 3:1 | INTID | R | 0h | Interrupt Type 7h Reserved
6h Character timeout indication (priority 2)
4h-5h Reserved
3h Receiver line status (priority 1, highest)
2h Receiver data available (priority 2)
1h Transmitter holding register empty
(priority 3)
0h Reserved |
| 0 | IPEND | R | 1h | Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0. 1h No interrupts pending 0h Interrupts pending |