SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
cgr Register
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| Instance Name | Physical Address |
|---|---|
| ICSSM0 | 4802 6010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ICSS_STOP_ACK | ICSS_STOP_REQ | ICSS_PWR_IDLE | RESERVED | ||||
| R/W | R | R/W | NONE | ||||
| 1h | 0h | 1h | 0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BOTTOM_HALF_CLK_GATE_EN | TOP_HALF_CLK_GATE_EN | AUTO_SLICE1_CLK_GATE_EN | AUTO_SLICE0_CLK_GATE_EN | IEP_CLK_EN | IEP_CLK_STOP_ACK | |
| NONE | R/W | R/W | R/W | R/W | R/W | R | |
| 0h | 1h | 1h | 0h | 0h | 1h | 0h | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IEP_CLK_STOP_REQ | ECAP_CLK_EN | ECAP_CLK_STOP_ACK | ECAP_CLK_STOP_REQ | UART_CLK_EN | UART_CLK_STOP_ACK | UART_CLK_STOP_REQ | INTC_CLK_EN |
| R/W | R/W | R | R/W | R/W | R | R/W | R/W |
| 0h | 1h | 0h | 0h | 1h | 0h | 0h | 1h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTC_CLK_STOP_ACK | INTC_CLK_STOP_REQ | RESERVED | |||||
| R | R/W | NONE | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | ICSS_STOP_ACK | R/W | 1h | |
| 30 | ICSS_STOP_REQ | R | 0h | |
| 29 | ICSS_PWR_IDLE | R/W | 1h | |
| 28:22 | RESERVED | NONE | 0h | Reserved |
| 21 | BOTTOM_HALF_CLK_GATE_EN | R/W | 1h | |
| 20 | TOP_HALF_CLK_GATE_EN | R/W | 1h | |
| 19 | AUTO_SLICE1_CLK_GATE_EN | R/W | 0h | |
| 18 | AUTO_SLICE0_CLK_GATE_EN | R/W | 0h | |
| 17 | IEP_CLK_EN | R/W | 1h | |
| 16 | IEP_CLK_STOP_ACK | R | 0h | |
| 15 | IEP_CLK_STOP_REQ | R/W | 0h | |
| 14 | ECAP_CLK_EN | R/W | 1h | |
| 13 | ECAP_CLK_STOP_ACK | R | 0h | |
| 12 | ECAP_CLK_STOP_REQ | R/W | 0h | |
| 11 | UART_CLK_EN | R/W | 1h | |
| 10 | UART_CLK_STOP_ACK | R | 0h | |
| 9 | UART_CLK_STOP_REQ | R/W | 0h | |
| 8 | INTC_CLK_EN | R/W | 1h | |
| 7 | INTC_CLK_STOP_ACK | R | 0h | |
| 6 | INTC_CLK_STOP_REQ | R/W | 0h | |
| 5:0 | RESERVED | NONE | 0h | Reserved |