SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

9.2.14.1 GPMC_ECC_CONFIG Register (Offset = 1F4h) [reset = 1030h]

ECC configuration .

Table 5-1194 Instance Table

Instance Name	Physical Address
GPMC0	4840 01F4h

Figure 5-592 GPMC_ECC_CONFIG Name Register

Table 5-1195 GPMC_ECC_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:17	RESERVED_206	R	0h	Write 0's for future compatibility. Read returns 0
16	ECCALGORITHM	R/W	0h	ECC algorithm used 0x0: Hamming code 0x1: BCH code
15:14	RESERVED_205	R	0h	Write 0's for future compatibility. Read returns 0
13:12	ECCBCHTSEL	R/W	1h	Error correction capability used for BCH 0x0: up to 4 bits error correction [t = 4] 0x1: up to 8 bits error correction [t=8] 0x2: up to 16 bits error correction [t=16] 0x3: reserved
11:8	ECCWRAPMODE	R/W	0h	Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details
7	ECC16B	R/W	0h	Selects an ECC calculated on 16 columns 1 ECC calculated on 16 columns 0 ECC calculated on 8 columns
6:4	ECCTOPSECTOR	R/W	3h	Number of sectors to process with the BCH algorithm 0x0: 1 sector [512kB page] 0x1: 2 sectors ... 0x3: 4 sectors [2kB page] ... 0x7: 8 sectors [4kB page]
3:1	ECCCS	R/W	0h	Selects the CS where ECC is computed 7 Chip select 7 6 Chip select 6 5 Chip select 5 4 Chip select 4 3 Chip select 3 2 Chip select 2 1 Chip select 1 0 Chip select 0
0	ECCENABLE	R/W	0h	Enables the ECC feature 1 ECC enabled 0 ECC disabled