SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.9.2.10 GPMC_PREFETCH_CONFIG1 Register

9.2.10.1 GPMC_PREFETCH_CONFIG1 Register (Offset = 1E0h) [reset = 4000h]

Prefetch engine configuration 1 .

Table 5-1186 Instance Table

Instance Name	Physical Address
GPMC0	4840 01E0h

Figure 5-588 GPMC_PREFETCH_CONFIG1 Name Register

31	30	29	28	27	26	25	24
RESERVED_221	CYCLEOPTIMIZATION			ENABLEOPTIMIZEDACCESS	ENGINECSSELECTOR
R	R/W			R/W	R/W
0h	0h			0h	0h
23	22	21	20	19	18	17	16
PFPWENROUNDROBIN	RESERVED_224			PFPWWEIGHTEDPRIO
R/W	R			R/W
0h	0h			0h
15	14	13	12	11	10	9	8
RESERVED_220	FIFOTHRESHOLD
R	R/W
0h	40h
7	6	5	4	3	2	1	0
ENABLEENGINE	RESERVED_223	WAITPINSELECTOR		SYNCHROMODE	DMAMODE	RESERVED_222	ACCESSMODE
R/W	R	R/W		R/W	R/W	R/W	R/W
0h	0h	0h		0h	0h	0h	0h

Table 5-1187 GPMC_PREFETCH_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED_221	R	0h	Write 0's for future compatibility. Read returns 0
30:28	CYCLEOPTIMIZATION	R/W	0h	Define the number of GPMC.FCLK cycles to be substracted from RdCycleTime, WrCycleTime, AccessTime, CSRdOffTime, CSWrOffTime, ADVRdOffTime, ADVWrOffTime, OEOffTime, WEOffTime [0x0 corresponds to 0 GPMC.FCLK cycle, 0x1 corresponds to 1 GPMC.FCLK cycle, &, 0x7 corresponds to 7 GPMC.FCLK cycles]
27	ENABLEOPTIMIZEDACCESS	R/W	0h	Enables access cycle optimization 1 Access cycle optimization is enabled 0 Access cycle optimization is disabled
26:24	ENGINECSSELECTOR	R/W	0h	Selects the CS where Prefetch Postwrite engine is active [0x0 corresponds toCS0, 0x1 corresponds to CS1, &, 0x7 corresponds to CS7]
23	PFPWENROUNDROBIN	R/W	0h	Enables the PFPW RoundRobin arbitration 1 Prefetch Postwrite engine round robin arbitration is enabled 0 Prefetch Postwrite engine round robin arbitration is disabled
22:20	RESERVED_224	R	0h	Write 0's for future compatibility. Read returns 0
19:16	PFPWWEIGHTEDPRIO	R/W	0h	When an arbitration occurs between a direct memory access and a PFPW engine access, the direct memory access is always serviced. If the PFPWEnRoundRobin is enabled, 0x0 means : the next access is granted to the PFPW engine, 0x1 means : the two next accesses are granted to the PFPW engine, ..., 0xF means : the 16 next accesses are granted to the PFPW engine.
15	RESERVED_220	R	0h	Write 0's for future compatibility. Read returns 0
14:8	FIFOTHRESHOLD	R/W	40h	Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request [0x00 corresponds to 0 byte, 0x01 corresponds to 1 byte, &, 0x40 corresponds to 64 bytes]
7	ENABLEENGINE	R/W	0h	Enables the Prefetch Postwite engine 1 Prefetch Postwrite engine is enabled 0 Prefetch Postwrite engine is disabled
6	RESERVED_223	R	0h	Write 0's for future compatibility. Read returns 0
5:4	WAITPINSELECTOR	R/W	0h	Select which wait pin edge detector should start the engine in synchronized mode 3 Selects Wait3EdgeDetection 2 Selects Wait2EdgeDetection 1 Selects Wait1EdgeDetection 0 Selects Wait0EdgeDetection
3	SYNCHROMODE	R/W	0h	Selects when the engine starts the access to CS 1 Engine starts the access to CS as soon as StartEngine is set AND wait to non wait edge detection on the selected wait pin 0 Engine starts the access to CS as soon as StartEngine is set
2	DMAMODE	R/W	0h	Selects interrupt synchronization or DMA request synchronization 1 DMA request synchronization is enabled.A DMA request protocol is used. 0 Interrupt synchronization is enabled. Only interrupt line will be activated on FIFO threshold crossing.
1	RESERVED_222	R/W	0h	Write 0's for future compatibility. Read returns 0
0	ACCESSMODE	R/W	0h	Selects pre-fetch read or write posting accesses 1 Write posting mode 0 Pre-fetch read mode