SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.2.2.1 MSS_DCC_DCCGCTRL Register

2.2.1.1 MSS_DCC_DCCGCTRL Register (Offset = 0h) [reset = 5555h]

Starts / stops the counters. Clears the error signal.

Table 5-858 Instance Table

Instance Name	Physical Address
DCC0	52B0 0000h
DCC1	52B0 1000h
DCC2	52B0 2000h
DCC3	52B0 3000h

Figure 5-428 MSS_DCC_DCCGCTRL Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
DONEENA				SINGLESHOT
R/W				R/W
5h				5h
7	6	5	4	3	2	1	0
ERRENA				DCCENA
R/W				R/W
5h				5h

Table 5-859 MSS_DCC_DCCGCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:16	RESERVED	NONE	0h	Reserved
15:12	DONEENA	R/W	5h	The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in DCCSTAT register. User, privilege, and debug mode (read): 0101= the done signal is disabled others = the done signal is enabled Privilege and debug mode (write): 0101= Disable done signal generation others 1010 = Enable done signal generation. It is recommended to write 1010 to enable each feature to avoid single soft errors.
11:8	SINGLESHOT	R/W	5h	The SINGLESHOT bit enables/disables repetitive operation of the DCC. User, privilege, and debug mode (read): 1010= stop counting when counter0 and valid0 both reach zero 1011= stop counting when counter1 reaches zero others = continuously repeat (until error) Privilege and debug mode (write): 1010= stop counting when counter0 and valid0 both reach zero 1011= stop counting when counter1 reaches zero others = continuously repeat (until error)
7:4	ERRENA	R/W	5h	The ERRENA bit enables/disables the error signal. User, privilege, and debug mode (read): 0101= the error signal is disabled others = the error signal is enabled Privilege and debug mode (write): 0101= disable error signal generation others 1010 = enable error signal generation. It is recommended to write 1010 to enable each feature to avoid single soft errors.
3:0	DCCENA	R/W	5h	The DCCENA bit starts and stops the operation of the dcc. User, privilege, and debug mode (read): 0101= counters are stopped others = counters are running Privilege and debug mode (write): 0101= stop counters and error-checking others 1010 = load the counters with their seed values and begin counting. It is recommended to write 1010 to enable each feature to avoid single soft errors.