SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.404 CPSW_NC_ALE_POLICECFG7 Register

1.2.404.1 CPSW_NC_ALE_POLICECFG7 Register (Offset = 3E11Ch) [reset = 0h]

The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time. If the counter is positive the packet will be marked GREEN, else it can be YELLOW or RED based on the PIR counter. If only this counter is used (aka pir_idle_inc_val==0) Packet are marked YELLOW or GREEN based on CIR counter only.

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Table 5-808 Instance Table

Instance Name	Physical Address
CPSW0	5283 E11Ch

Figure 5-404 CPSW_NC_ALE_POLICECFG7 Name Register

31	30	29	28	27	26	25	24
CIR_IDLE_INC_VAL
R/W
0h
23	22	21	20	19	18	17	16
CIR_IDLE_INC_VAL
R/W
0h
15	14	13	12	11	10	9	8
CIR_IDLE_INC_VAL
R/W
0h
7	6	5	4	3	2	1	0
CIR_IDLE_INC_VAL
R/W
0h

Table 5-809 CPSW_NC_ALE_POLICECFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:0	CIR_IDLE_INC_VAL	R/W	0h	Committed Information Idle Increment Value - The number added to the CIR counter every clock cycle. If zero the CIR counter is disabled and packets will never be marked or processed as YELLOW.