SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.135 CPSW_NC_ETH_MAC_PN_EST_CONTROL_REG_K Register

1.2.135.1 CPSW_NC_ETH_MAC_PN_EST_CONTROL_REG_K Register (Offset = 22060h) [reset = 0h]

Enet Port N EST CONTROL

Offset = Base + (k * 1000h); where k = 0 to 1d

Table 5-270 Instance Table

Instance Name	Physical Address
CPSW0	5282 2060h + formula

Figure 5-135 CPSW_NC_ETH_MAC_PN_EST_CONTROL_REG_K Name Register

31	30	29	28	27	26	25	24
RESERVED						EST_FILL_MARGIN
NONE						R/W
0h						0h
23	22	21	20	19	18	17	16
EST_FILL_MARGIN
R/W
0h
15	14	13	12	11	10	9	8
EST_PREMPT_COMP							EST_FILL_EN
R/W							R/W
0h							0h
7	6	5	4	3	2	1	0
EST_TS_PRI			EST_TS_ONEPRI	EST_TS_FIRST	EST_TS_EN	EST_BUFSEL	EST_ONEBUF
R/W			R/W	R/W	R/W	R/W	R/W
0h			0h	0h	0h	0h	0h

Table 5-271 CPSW_NC_ETH_MAC_PN_EST_CONTROL_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31:26	RESERVED	NONE	0h	Reserved
25:16	EST_FILL_MARGIN	R/W	0h	EST Fill Margin - Sets the fill margin (in bytes) required to ensure that the Ethernet wire is clear so that the timed EST express packet can egress at the correct required time. Setting this value too high will put an unnecessary gap on the wire. Setting this value too low will cause the express packet to egress at a time later than intended (pushed out by non express traffic that did not have sufficient time to finish).
15:9	EST_PREMPT_COMP	R/W	0h	EST Prempt Comparison Value - When the count in a zero allow is less than or equal to this value in bytes (times 8), prempt packets are cleared from the wire. This is the prempt clear margin value.
8	EST_FILL_EN	R/W	0h	EST Fill Enable - Enable EST fill mode when set.
7:5	EST_TS_PRI	R/W	0h	EST Timestamp Express Priority - Selects the express priority that timestamp(s) will be generated on when pn_est_ts_onepri is set.
4	EST_TS_ONEPRI	R/W	0h	EST Timestamp One Express Priority - When set, timestamps are only enabled on packets on the express priority selected by pn_est_ts_pri. When cleared to zero, express packet selection for timestamps is independent of priority.
3	EST_TS_FIRST	R/W	0h	EST Timestamp First Express Packet only - Generate a timestamp only on the first selected express packet in each EST time interval when express timestamps are enabled. (If pn_est_ts_onepri is also set then the timestamp is generated only on the first packet on pn_est_ts_pri).
2	EST_TS_EN	R/W	0h	EST Timestamp Enable - Enable express timestamps (when est_en and pn_est_port_en are set).
1	EST_BUFSEL	R/W	0h	EST Buffer Select - If pn_est_onebuf is cleared, this bit selects the upper (when set) or the lower (when cleared) 64-word fetch buffer. The actual fetch buffer used changes only at the start of the EST time interval and can be read in the Enet_Pn_FIFO_Status register pn_est_bufact bit.
0	EST_ONEBUF	R/W	0h	EST One Fetch Buffer - When set indicates that all 128 fetch words are used in one buffer. When cleared, indicates that the 128 fetch words are split into two 64-word fetch buffers. The pn_est_bufsel selects the buffer to be used when pn_est_onebuf is cleared to zero. Two buffers allows software to change a buffer while the hardware is using the other buffer.