SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.15.1 CPSW_MDIO_LINK_INT_MASKED_REG Register (Offset = F14h) [reset = 0h]

MDIO Link Interrupt Masked Register

Table 5-30 Instance Table

Instance Name	Physical Address
CPSW0	5280 0F14h

Figure 5-15 CPSW_MDIO_LINK_INT_MASKED_REG Name Register

Table 5-31 CPSW_MDIO_LINK_INT_MASKED_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:2	RESERVED	NONE	0h	Reserved
1:0	LINKINTMASKED	R/W	0h	MDIO link change interrupt masked value. Normal mode operation: When asserted, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. These masked interrupt bits are the MDIO_LINKINT[1:0] pin values. MDIO link change interrupt masked value. State Change Mode operation: The linkintmasked[0] bit will be asserted when linkintraw[0] is asserted and when the linkintmaskset bit is set to 1. Writing a 1 will clear linkintmasked[0] (and the MDIO_LINKINT[0] output) and writing 0 has no effect. The linkintmasked[1] bit is not used in State Change Mode (MDIO_LINKINT[1] is therefore also unused in State Change Mode).