SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line.
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| Instance Name | Physical Address |
|---|---|
| WDT0 | 5210 00BCh |
| WDT1 | 5210 10BCh |
| WDT2 | 5210 20BCh |
| WDT3 | 5210 30BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| COMP3CLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| COMP3CLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| COMP3CLR | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COMP3CLR | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | COMP3CLR | R/W | 0h | COMP3CLR: Compare 3 Clear. This registers holds a compare value, which is compared with the counter selected in the compare control logic. If the Free Running Counter matches the compare value, the Compare 3 interrupt or DMA request line is cleared. User and privilege mode [read]: current compare value Privilege mode [write]: update of the compare register with a new compare value Note: Reset behavior A reset does not generate a compare match, since the compare logic will only be active, when the associated counter block is enabled. |