SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation.
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| Instance Name | Physical Address |
|---|---|
| WDT0 | 5210 0084h |
| WDT1 | 5210 1084h |
| WDT2 | 5210 2084h |
| WDT3 | 5210 3084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED14 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED14 | CLEAROVL1INT | CLEAROVL0INT | CLEARTBINT | ||||
| R/W | R/W | R/W | R/W | ||||
| 0h | 0h | 0h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED13 | CLEARDMA3 | CLEARDMA2 | CLEARDMA1 | CLEARDMA0 | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED12 | CLEARINT3 | CLEARINT2 | CLEARINT1 | CLEARINT0 | |||
| R/W | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED14 | R/W | 0h | Reserved. Reads return 0 and writes have no effect |
| 18 | CLEAROVL1INT | R/W | 0h | CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 17 | CLEAROVL0INT | R/W | 0h | CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 16 | CLEARTBINT | R/W | 0h | CLEARTBINT: CLEAR Timebase Interrupt. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 15:12 | RESERVED13 | R/W | 0h | Reserved. Reads return 0 and writes have no effect |
| 11 | CLEARDMA3 | R/W | 0h | CLEARDMA3: CLEAR Compare DMA Request 3. User and privilege mode [read]: 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable DMA request |
| 10 | CLEARDMA2 | R/W | 0h | CLEARDMA2: CLEAR Compare DMA Request 2. User and privilege mode [read]: 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable DMA request |
| 9 | CLEARDMA1 | R/W | 0h | CLEARDMA1: CLEAR Compare DMA Request 1. User and privilege mode [read]: 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable DMA request |
| 8 | CLEARDMA0 | R/W | 0h | CLEARDMA0: CLEAR Compare DMA Request 0. User and privilege mode [read]: 0 = DMA request is disabled 1 = DMA request is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable DMA request |
| 7:4 | RESERVED12 | R/W | 0h | Reserved. Reads return 0 and writes have no effect |
| 3 | CLEARINT3 | R/W | 0h | CLEARINT3: CLEAR Compare Interrupt 3. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 2 | CLEARINT2 | R/W | 0h | CLEARINT2: CLEAR Compare Interrupt 2. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 1 | CLEARINT1 | R/W | 0h | CLEARINT1: CLEAR Compare Interrupt 1. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |
| 0 | CLEARINT0 | R/W | 0h | CLEARINT0: CLEAR Compare Interrupt 0. User and privilege mode [read]: 0 = interrupt is disabled 1 = interrupt is enabled Privilege mode [write]: 0 = leaves the corresponding bit unchanged 1 = disable interrupt |