SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Time out counter preload register.
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| Instance Name | Physical Address |
|---|---|
| R5SS0 | 5350 0008h |
| R5SS1 | 5351 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TO_PRELOAD | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TO_PRELOAD | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TO_PRELOAD | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TO_PRELOAD | |||||||
| R/W | |||||||
| FFFFFFFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TO_PRELOAD | R/W | FFFFFFFFh | Self test time out preload [RWP - Read, Priviledge Mode Write only] This register contains the total number of STC clock cycles it will take before a self-test timeout error will be triggered after the initiation of the self-test run. This is a fail safe feature to avoid system hang-up situation on account of any run away self test issues. This register should be loaded with a meaningful count value for this feature to be effective. This register value [preload count value] gets loaded into the self test timeout down counter whenever a self test run is initiated [ST_ENA is enabled]. and gets disabled on completion of a self test run. |