SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Self test Global control Reg1.
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| Instance Name | Physical Address |
|---|---|
| R5SS0 | 5350 0004h |
| R5SS1 | 5351 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| NU2 | |||||||
| NU2 | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| NU2 | |||||||
| NU2 | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| NU2 | SEG0_CORE_SEL | ||||||
| NU2 | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NU3 | CODEC_SPREAD_MODE | LP_SCAN_MODE | ROM_ACCESS_INV | ST_ENA_B4 | |||
| R | R/W | R/W | R/W | R/W | |||
| 0h | 0h | 1h | 0h | 5h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:12 | NU2 | NU2 | 0h | Reserved bits |
| 11:8 | SEG0_CORE_SEL | R/W | 0h | Selects the Segment0 CORE for self test [RWP - Read, Priviledge Mode Write only] Select the Segment0 CORE for Self -Test 0001= Select CORE for selftest Other = CORE not selected. |
| 7 | NU3 | R | 0h | Reserved bits |
| 6 | CODEC_SPREAD_MODE | R/W | 0h | Codec Spread Mode control signal [RWP - Read, Priviledge Mode Write only] This bit is used to configure the codec in spread / X-OR mode. 1 = Spread mode 0 = XOR mode |
| 5 | LP_SCAN_MODE | R/W | 1h | LP scan mode [RWP - Read, Priviledge Mode Write only] This bit is used to decide the scan configuration: 1 = Operates in Low Power Scan Mode. 0 = Operates in Normal Scan Mode. |
| 4 | ROM_ACCESS_INV | R/W | 0h | Rom access inversion mode [RWP - Read, Priviledge Mode Write only] - NOT SUPPORTED |
| 3:0 | ST_ENA_B4 | R/W | 5h | Self test enable key [RWP - Read, Priviledge Mode Write only] 1010= Self test run enabled All values other than 1010= Self test run disabled |