SPRUJ42 User guide | 德州仪器 TI.com.cn

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.56.1 VIM1_INTVECTOR_Q Register (Offset = 2000h) [reset = 0h]

Interrupt Q Vector Register (Q is 0 to 255) Address formula = 50F00000h + Offset + Q x 4h

Table 4-130 Instance Table

Instance Name	Physical Address
R5SS0	50F0 2000h
R5SS1	50F0 2000h

Figure 4-56 VIM1_INTVECTOR_Q Name Register

Table 4-131 VIM1_INTVECTOR_Q Register Field Descriptions

Bit	Field	Type	Reset	Description
31:2	ADDR	R/W	0h	This is the 32-bit Vector Address associated with interrupt Q. It is the address that will be reflected in the IRQ Vector Address [Base Address + 0x18] or FIQ Vector Address [Base Address + 0x1C] and the VECADDR pin when interrupt Q is the active interrupt. Internally, these values are kept in a RAM. The FIQ and IRQ state machines have priority access to this RAM. Writes to this register will be piped internally, but further writes to the MMR interface may be stalled until this write has a chance to complete in the RAM. The new Vector Address will not take effect until this write completes to the RAM. In order to tell if this write has completed, software may read this register back. That read will not be able to complete unless the write has landed. Reads to this register will stall the MMR interface until the read is able to be completed at the RAM.
1:0	RES20	R	0h	Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned.