SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

15.2.31.1 MMC_PVINITSD Register (Offset = 260h) [reset = 0h]

Preset Value for Initialization and Default Speed modes.

Table 5-1824 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0260h

Figure 5-900 MMC_PVINITSD Name Register

Table 5-1825 MMC_PVINITSD Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	DSDS_SEL	R	0h	Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 3 Driver Type D is Selected. 2 Driver Type C is Selected. 1 Driver Type A is Selected. 0 Driver Type B is Selected.
29:27	RESERVED1	R	0h
26	DSCLKGEN_SEL	R	0h	Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator. 1 Programmable Clock Generator. 0 Host Controller Ver2.00 Compatible Clock Generator.
25:16	DSSDCLK_SEL	R	0h	SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.
15:14	INITDS_SEL	R	0h	Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling. 3 Driver Type D is Selected 2 Driver Type C is Selected 1 Driver Type A is Selected 0 Driver Type B is Selected
13:11	RESERVED	R	0h
10	INITCLKGEN_SEL	R	0h	Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator. 1 Programmable Clock Generator. 0 Host Controller Ver2.00 Compatible Clock Generator.
9:0	INITSDCLK_SEL	R	0h	SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set SDCLK Frequency Select in the Clock Control Register is described by a host system.